Method and device for generating low-jitter clock

1. A method for generating a low jitter low-speed clock, comprising:

step A: selecting a time delay Δt for delaying the high-speed clock cycles;

step B: according to the frequency f H of the high-speed clock cycles, the frequency f L of the current low-speed clock cycles, the frequency f Q of the targeted low-speed clock cycles to be obtained after the frequency division is performed, and the time delay Δt got from the step A, calculating the time interval T between two adjacent insertions of the time delay Δt in the high-speed clock cycles, the total number N of the time delay Δts required to be inserted, and times of the multiples of frequency division;

step C: within each time frame corresponding to a low-speed clock cycle, inserting a time delay Δt in a single period of high-speed clock cycles at the time interval T until number N time delay Δts are inserted;

step D: according to the times of the multiples of frequency division from the step B, performing the frequency division operation on the high-speed clock cycles from the step C to obtain the low jitter low-speed clock cycles.

2. The method according to claim 1 , wherein, the time delay Δt is a positive value or a negative value; and

said inserting one time delay Δt in the single period of the high-speed clock cycles is: adding or deducting one absolute value of the time delay Δt in the single period of the high-speed clock cycles.

3. The method according to claim 2 , wherein, the absolute value of the time delay Δt is less than a value of one high-speed clock period cycles.

4. The method according to claim 2 , wherein, said adding or deducting one absolute value of the time delay Δt in the single period of the high-speed clock cycles is based on:

if a frequency of the low-speed clock cycles required to be obtained is less than a clock frequency obtained after an integer frequency division is performed on the high-speed clock cycles, adding one absolute value of the time delay Δt in the single period of the high-speed clock cycles; and

if the frequency of the low-speed clock cycles required to be obtained is greater than the clock frequency obtained after the integer frequency division is performed on the high-speed clock cycles, deducting one absolute value of the time delay Δt in the single period of the high-speed clock cycles.

5. An apparatus for generating a low jitter low-speed clock, comprising a clock cycle adjustment module, wherein,

said clock cycle adjustment module is configured to insert a time delay Δt in each single period of low-speed clock cycles to finely adjust the corresponding high-speed clock cycles, and then perform frequency division operation on the adjusted high-speed clock cycles to obtain the low-jitter low-speed clock cycles;

said clock cycle adjustment module further comprising a delay module, a frequency division module and a calculation module; wherein,

said delay module is configured to allow users to select a time delay Δt for delaying the high-speed clock cycles, and notify the selection result to the calculation module; and after receiving the calculation results from the calculation module, within each time frame corresponding to a low-speed clock cycle, insert a time delay Δt in a single period of high-speed clock cycles at the time interval T until number N time delay Δts are inserted, where in the time interval T and the number N are the calculation results from the calculation module; and then said delay module transmit the adjusted high-speed clock cycles to the frequency division module;

said calculation module is configured to, according to the frequency f H of the high-speed clock cycles, the frequency f L of the current low-speed clock cycles, the frequency f O of the targeted low-speed clock cycles to be obtained after the frequency division is performed, and the time delay Δt provided by the delay module, calculate the time interval T between two adjacent insertions of the time delay Δt in the high-speed clock cycles, the total number N of the time delay Δts required to be inserted, and times of the multiples of frequency division; and then send the time interval T and the total number N to the delay module, and send the times of the multiples of frequency division to the frequency division module;

said frequency division module is configured to, according to the times of the multiples of frequency division received from the calculation module, perform the frequency division operation on the high-speed clock cycles that sent from the delay module to obtain the low jitter low-speed clock cycles.

6. The apparatus according to claim 5 , wherein, the absolute value of the time delay Δt is less than the value of one high-speed clock cycle period.

7. The method according to claim 1 , wherein, the time delay Δt is a positive value or a negative value; and

correspondingly, said inserting one time delay Δt in the single period of the high-speed clock cycles is: adding or deducting one absolute value of the time delay Δt in the single period of the high-speed clock cycles.

8. The method according to claim 7 , wherein, the absolute value of the time delay Δt is less than a value of one high-speed clock cycles period.

9. The method according to claim 7 , wherein, said adding or deducting one absolute value of the time delay Δt in the single period of the high-speed clock cycles is based on:

if a frequency of the low-speed clock cycles required to be obtained is less than a clock cycles frequency obtained after an integer frequency division is performed on the high-speed clock cycles, adding one absolute value of the time delay Δt in the single period of the high-speed clock cycles; and

if the frequency of the low-speed clock cycles required to be obtained is greater than the clock frequency obtained after the integer frequency division is performed on the high-speed clock cycles, deducting one absolute value of the time delay Δt in the single period of the high-speed clock cycles.

10. The apparatus according to claim 5 , wherein, an absolute value of the time delay Δt is less than a value of one high-speed clock cycle period.