IP Library Granted Patent US 9,025,791
Granted Patent B2
US 9,025,791 · App. 13/512,593 · Granted May 5, 2015

Pop-up noise reduction in a device

Inventors: Ankit Seedher (Banaglore, IN); Raja J. Prabhu (Bangalore, IN); Shyam S. Somayajula (Bangalore, IN)
Assignee: ST-Ericsson SA
H03F3/217H03F1/305
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Quick Facts
Patent No.
US 9,025,791
App. No.
13/512,593
Granted
May 5, 2015
Kind
B2
Abstract

A device implementing a scheme for reduction of pop-up noise is disclosed. The device comprises an audio sub-system ( 100 ) having an integrator ( 112 ) for amplifying an input signal ( 133 ) and a modulation circuit ( 114 ) including one or more comparators. The audio subsystem ( 100 ) is further provided with a feedback loop ( 142 ) across the integrator ( 112 ) and the modulation circuit ( 114 ) to calibrate an offsets outputs of the integrator ( 112 ) and the modulation circuit ( 114 ). The feedback loop ( 142 ) includes an integrator-offset loop ( 202 ) across the integrator ( 112 ) to calibrate an offset ( 136 ) in the output of the integrator ( 112 ), and an offset calibration loop ( 302 ) across the modulation circuit ( 114 ) to calibrate an offset ( 140 ) in the output of the modulation circuit ( 114 ).

Claims (39)

1. A device comprising:

an integrator operative to amplify an input signal;

a modulation circuit operative to modulate an amplified input signal received from the integrator;

an integrator-offset feedback loop selectively connected across the integrator and operative to bias the integrator input so as to counter an offset voltage in the integrator; and

a comparator-offset feedback loop, including a capacitor, selectively connected across the modulation circuit and operative to bias the modulation circuit input so as to counter a comparator offset voltage in the modulation circuit.

2. The device as claimed in claim 1 , further comprising a driver circuit coupled to the modulation circuit, wherein the driver circuit is placed in a high impedance state during an operation of the feedback loop.

3. The device as claimed in claim 2 , wherein the comparator-offset loop comprises capacitors operative to charge to a voltage that counters the comparator offset voltage in the modulation circuit.

4. The device as claimed in claim 3 , wherein the comparator-offset loop is connected across the modulation circuit for a sufficient duration to charge the capacitors to the counter voltage prior to enabling the driver circuit.

5. The device as claimed in claim 1 , wherein the device further comprises at least one controller coupled to the integrator-offset loop, wherein the controller senses an offset detected by the integrator-offset loop and provides an offset-cancellation signal to nullify the offset.

6. The device as claimed in claim 5 , wherein the controller is configured to power down the modulation circuit during an operation of the integrator-offset loop.

7. The device as claimed in claim 1 , wherein the device is selected from a group consisting of home entertainment devices, audio players, video players, amplification systems, computing devices, laptops, and communication devices.

8. An audio subsystem comprising:

an integrator operative to amplify an input signal;

an integrator-offset feedback loop selectively connected across the integrator and operative to detect an offset in an output of the integrator; and

a controller coupled to the integrator-offset loop and operative to sense the offset detected by the integrator-offset loop, wherein the controller is further operative to generate an offset-cancellation signal, based on the detected offset, to nullify the offset.

9. The audio subsystem as claimed in claim 8 , further comprising:

a modulation circuit operative to receive the amplified input signal, wherein the modulation circuit is operative to modulate the amplified input signal; and

a driver circuit coupled to the modulation circuit;

wherein the modulation circuit is powered down and the driver circuit is put in a high impedance state during an operation of the integrator-offset loop.

10. The audio subsystem as claimed in claim 8 , wherein the controller is coupled to at least one summing amplifier to provide the offset-cancellation signal to an input of the integrator.

11. The audio subsystem as claimed in claim 8 , wherein the controller includes a memory unit to store the offset-cancellation signal.

12. The audio subsystem as claimed in claim 8 , wherein the integrator-offset loop comprises a switch controlled by the controller to enable and disable the integrator-offset loop.

13. An audio subsystem comprising:

a modulation circuit operative to modulate an input signal;

at least one comparator-offset feedback loop, including a capacitor, selectively connected across the modulation circuit and operative to counter an offset voltage in an output of the modulation circuit; and

at least one capacitor coupled to the comparator-offset loop, wherein the capacitor is charged to a potential equal to a negative value of the offset voltage to nullify the offset voltage.

14. The audio subsystem as claimed in claim 13 , further comprising a driver circuit coupled to the modulation circuit, wherein the driver circuit is placed in a high impedance state during an operation of the comparator-offset loop.

15. The audio subsystem as claimed in claim 13 , wherein the comparator-offset loop comprises a switch configured to enable the comparator-offset loop for an offset correction time interval.

16. The audio subsystem as claimed in claim 13 , wherein the modulation circuit comprises one or more comparators.

17. A method of calibrating an audio circuit to reduce pop-up noise, comprising:

setting a driver circuit in a high impedance state;

enabling an integrator-offset feedback loop selectively connected across an integrator;

detecting an offset in an output signal of the integrator;

generating offset-cancellation signals based on the detected offset; and

providing the offset-cancellation signals to an input of the integrator.

18. The method as claimed in claim 17 , wherein detecting the offset comprises powering down a modulation circuit.

19. The method as claimed in claim 17 , further comprising:

powering up a modulation circuit; and

countering an offset voltage in an output of the modulation circuit by charging capacitors in a feedback loop to a potential equal to a negative value of the offset voltage.

Assignments (3)
STATUS CHANGE-ENTITY IN LIQUIDATION Recorded Feb 2, 2016
From: ST-ERICSSON SA
To: ST-ERICSSON SA, EN LIQUIDATION
Reel/Frame 037739/0493 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2014
From: ST-ERICSSON INDIA PVT. LTD.
To: ST-ERICSSON SA
Reel/Frame 033305/0863 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 4, 2013
From: PRABHU, RAJA J.; SEEDHER, ANKIT; SOMAYAJULA, SHYAM
To: ST-ERICSSON SA; ST-ERICSSON INDIA PVT. LTD.
Reel/Frame 031347/0559 →
Continuity (1)
Related Publication 20120274399A1 · Nov 1, 2012