Optoelectronic semiconductor chip and method for fabrication thereof

1. A method of fabricating an optoelectronic semiconductor chip, the method comprising:

epitaxially depositing a first semiconductor layer sequence over a growth substrate, the first semiconductor layer sequence comprising an ESD layer, wherein the first semiconductor layer sequence is deposited at a growth temperature at which V-pits occur in a high density in the ESD layer, wherein the ESD layer is based on GaN, and wherein the ESD layer is grown at a growth temperature below 900° C. by using triethylgallium precursor with a nitrogen carrier gas; and

epitaxially depositing a second semiconductor layer sequence onto the first semiconductor layer sequence, the second semiconductor layer sequence comprising an active region.

2. The method according to claim 1 , wherein the growth substrate comprises sapphire.

3. The method according to claim 1 , wherein the method is used to fabricate an optoelectronic semiconductor chip comprising:

the first semiconductor layer sequence comprising a plurality of microdiodes; and

the second semiconductor layer sequence comprising the active region,

wherein the first semiconductor layer sequence and the second semiconductor layer sequence are based on a nitride compound semiconductor material,

wherein the microdiodes form an ESD protection for the active region, and

wherein a majority of the microdiodes have a breakdown behavior of the same type.

4. The method according to claim 1 , wherein the V-pits are formed on dislocation lines in a clearly defined ESD layer.

5. A method for fabricating an optoelectronic semiconductor chip, the method comprising:

epitaxially depositing a first semiconductor layer sequence over a growth substrate; and

epitaxially depositing a second semiconductor layer sequence onto the first semiconductor layer sequence,

wherein the first semiconductor layer sequence comprises an ESD layer that is deposited at a growth temperature at which V-pits occur in a high density in the ESD layer,

wherein the second semiconductor layer sequence comprises an active region,

wherein the ESD layer is based on GaN, the ESD layer being grown at a growth temperature between 790° C. and 870° C. inclusive by using a triethylgallium precursor with a nitrogen carrier gas, and

wherein the majority of the V-pits have similar dimensions.

6. A method for fabricating an optoelectronic semiconductor chip, the method comprising:

epitaxially depositing a first semiconductor layer sequence over a growth substrate; and

epitaxially depositing a second semiconductor layer sequence onto the first semiconductor layer sequence,

wherein the first semiconductor layer sequence comprises an ESD layer that is deposited at a growth temperature at which V-pits occur in a high density in the ESD layer,

wherein the second semiconductor layer sequence comprises an active region,

wherein the ESD layer is based on GaN, the ESD layer being grown at a growth temperature of at least 790° by using a triethylgallium precursor with a nitrogen carrier gas, and

wherein the density of the V-pits is at least 5×10 8 /cm 2 .

7. The method according to claim 1 , wherein the density of the V-pits is at least 5×10 8 /cm 2 .

8. The method according to claim 1 , wherein the density of the V-pits is at most 5×10 9 /cm 2 .

9. The method according to claim 1 , wherein a growth time of the ESD layer is chosen such that the ESD layer has a thickness that is between half and three times a thickness of the active region.

10. The method according to claim 4 , wherein the ESD layer has a thickness of at least 80 nm and at most 150 nm.

11. The method according to claim 1 , wherein at least 75% of the V-pits have similar dimensions.