CONTROLLER FOR DETECTING AND CORRECTING AN ERROR WITHOUT A BUFFER, AND METHOD FOR OPERATING SAME
An operational method of a controller for a flash memory may include receiving target data read out from the flash memory, outputting the received target data to a main memory, and generating an error detection syndrome related to the received target data after or simultaneously with completion of the output of the target data.
1 . An operational method of a controller for a flash memory, the operational method comprising:
receiving target data read out from the flash memory;
outputting the received target data to a main memory; and
generating an error detection syndrome related to the received target data, after or simultaneously with completion of the output of the target data.
2 . The operational method of claim 1 , wherein the outputting comprises outputting the received target data simultaneously with the receiving of the target data, without using a buffer provided in the controller to store the received target data.
3 . The operational method of claim 1 , further comprising:
reading out the target data again based on the error detection syndrome.
4 . The operational method of claim 3 , further comprising:
calculating, before the target data is read out again, at least one of a location of an error and a corrected value with respect to the error when the error detection syndrome indicates presence of the error in the received target data.
5 . The operational method of claim 4 , further comprising:
outputting new target data to the main memory by inserting the corrected value in the target data read out again.
6 . The operational method of claim 1 , wherein the generating comprises starting generation of the error detection syndrome using Bose, Chaudhuri, and Hocquenghem (BCH) codes during reception of the target data.
7 . The operational method of claim 4 , wherein the reading comprises reading again part of the target data that includes the error.
8 . A non-transitory computer-readable recording medium storing a program to cause a computer to implement the method of claim 1 .
9 . A controller for a flash memory, the controller comprising:
an interface to receive target data read out from the flash memory and to output the received target data to a main memory; and
an error detector to generate an error detection syndrome with respect to the received target data, after or simultaneously with completion of the output of the target data.
10 . The controller of claim 9 , wherein the interface outputs the received target data directly to the main memory without using a buffer provided in the controller to store the received target data.
11 . The controller of claim 9 , further comprising a command generator to generate a command for reading out the target data again based on the error detection syndrome.
12 . The controller of claim 11 , wherein the error detector calculates, before the target data is read out again, at least one of a location of an error and a corrected value with respect to the error when the error detection syndrome indicates presence of the error in the received target data.
13 . The controller of claim 12 , wherein
the error detector generates a command for inserting the corrected value in the target data read out again so as to generate new target data, and
the interface outputs the new target data to the main memory.
14 . The controller of claim 9 , wherein the error detector starts generation of the error detection syndrome using Bose, Chaudhuri, and Hocquenghem (BCH) codes during reception of the target data.