Thin film transistor array panel and manufacturing method thereof
View Patent ↗A thin film transistor array panel is provided, which includes a plurality of gate lines, a plurality of common electrodes, a gate insulating layer covering the gate lines and the common electrodes, a plurality of semiconductor layers formed on the gate insulating layer, a plurality of data lines including a plurality of source electrodes and formed on the semiconductor layer, a plurality of drain electrodes formed on the semiconductor layer, and a plurality of pixel electrodes overlapping the common electrodes and connected to the drain electrodes. Because the common electrodes are made of ITON, IZON, or a-ITON, or a double layer of ITO/ITON, IZO/IZON, or a-a-ITO/a-ITON, when H2 or SiH4 are injected to form a silicon nitride (SiNX) layer on the common electrodes, the opaque metal Sn or Zn is not produced on the surfaces of the common electrode.
1. A method of manufacturing a thin film transistor array panel, comprising:
forming a gate line on a substrate;
forming a common electrode having a transparent conductive layer on the substrate;
depositing a gate insulating layer covering the gate line and the common electrode;
forming a semiconductor layer on the gate insulating layer;
forming a data line and a drain electrode on the gate insulating layer and the semiconductor layer; and
forming a pixel electrode connected to the drain electrode,
wherein the pixel electrode and the common electrode at least partially overlap each other; and
wherein the transparent conductive layer is comprised of indium tin oxide nitride (ITON), indium zinc oxide nitride (IZON), or amorphous indium tin oxide nitride (a-ITON).
2. The method of claim 1 , wherein the ITON, IZON, or a-ITON are formed by sputtering ITO, IZO, or a-ITO under a nitrogen atmosphere.
3. The method of claim 1 , wherein a thickness of the ITON, IZON, or a-ITON is in the range of 10-3,000 angstroms.
4. The method of claim 1 , wherein the transparent conductive layer is comprised of double layer structure of indium tin oxide/indium tin oxide nitride (ITO/ITON), indium zinc oxide/indium zinc oxide/indium zinc oxide nitride (IZO/IZON), or amorphous indium tin oxide/amorphous indium tin oxide nitride (a-ITO/a-ITON).
5. The method of claim 4 , wherein the formation of the double layer structure of ITO/ITON, IZO/IZON, or a-ITO/a-ITON comprises:
forming a first conductive layer of ITO, IZO, or a-ITO; and
forming a second layer of ITON, IZON, or a-ITON using reaction sputtering while injecting nitrogen gas.
6. The method of claim 4 , wherein the formation of the double layer structure of ITO/ITON, IZO/IZON, or a-ITO/a-ITON comprises:
forming a first conductive layer of ITO, IZO, or a-ITO; and
forming a second layer of ITON, IZON, or a-ITON using NH 3 plasma.
7. The method of claim 6 , wherein a thickness of the ITON, IZON, and a-ITON is in the range of 50-1,000 angstroms.