Apparatus and method for low noise amplification
View Patent ↗Embodiments provide an amplifier and a method for using and manufacturing said amplifier that incorporate an impedance matching stage, a feedback circuit, and a gain stage. The impedance matching stage is coupled to the feedback circuit wherein the feedback circuit provides a compensated second bias voltage for the impedance matching stage. The output of the impedance matching stage is used to set an input bias voltage for both the impedance matching stage and the gain stage. The output of the impedance matching stage is also used, together with the output of the gain stage, to produce an output of the amplifier. A signal reuse stage may be provided between the output of the impedance matching stage and the output of the amplifier.
1. An amplifier comprising:
an impedance matching stage coupled to an input of the amplifier, the output of the impedance matching stage providing a first, input bias voltage for the impedance matching stage;
a feedback circuit coupled to the output of the impedance matching stage and a first voltage source, the feedback circuit being configured to compensate a second bias voltage for the impedance matching stage; and
a gain stage coupled to the input of the amplifier, the output of the impedance matching stage providing an input bias voltage for the gain stage;
wherein an output of the gain stage and the output of the impedance matching stage are used to produce an output of the amplifier.
2. The amplifier of claim 1 , wherein the feedback circuit comprises an amplifier circuit, the output of the impedance matching stage being coupled to an inverting input of the amplifier circuit, the first voltage source being coupled to a non-inverting input of the amplifier circuit and the compensated second bias voltage for the impedance matching stage being set based on the amplifier circuit.
3. The amplifier of claim 1 , wherein the impedance matching stage comprises:
a feedback resistor coupled to the input of the amplifier and a first node;
a load component coupled to an output of the feedback circuit and the first node; and
a first NMOS transistor having a source, a gate and a drain, the gate being coupled to the input of the amplifier, the drain being coupled to the first node, the first node providing the output of the impedance matching stage.
4. The amplifier of claim 3 , wherein the load component comprises a PMOS transistor having a source, a gate and a drain, the gate of the PMOS transistor being coupled to the output of the feedback circuit to provide the compensated second bias voltage for the impedance matching stage, the drain of the PMOS transistor being coupled to the first node.
5. The amplifier of claim 4 , wherein the output of the feedback circuit is coupled to the gate of the PMOS transistor via a first resistor and the input of the feedback circuit is coupled to the first node via a second resistor.
6. The amplifier of claim 5 , wherein the gate of the PMOS transistor is coupled to the input of the amplifier via a first AC-coupling capacitor.
7. The amplifier of claim 4 , wherein transconductances of the PMOS transistor and the first NMOS transistor and the resistance of the feedback resistor are selected to match a desired source impedance.
8. The amplifier of claim 3 , wherein the gain stage comprises:
a second NMOS transistor having a source, a gate and a drain, the gate of the second NMOS transistor being coupled to the input of the amplifier, the drain of the second NMOS transistor comprising the output of the gain stage.
9. The amplifier of claim 1 , further comprising:
a signal coupling stage coupled to the output of the impedance matching stage, an output of the signal coupling stage being used together with the output of the gain stage to produce the output of the amplifier.
10. The amplifier of claim 9 , wherein the signal coupling stage comprises:
an NMOS transistor having a source, a gate and a drain, the gate being coupled to the output of the impedance matching stage, the source being coupled to the output of the gain stage.
11. The amplifier of claim 10 , wherein the gate of the NMOS transistor is coupled to a second voltage source via a resistor to bias the gate, the gate being coupled to the output of the impedance matching stage via an AC-coupling capacitor.
12. The amplifier of claim 1 , further comprising:
at least one current cascode located before the output of the amplifier.
13. The amplifier of claim 12 , wherein a first one of the at least one current cascode comprises:
an NMOS transistor having a source, a gate and a drain, the source being coupled to at least the output of the gain stage.
14. The amplifier of claim 13 , wherein a second one of the at least one current cascade is coupled to the first current cascode between the drain of the NMOS transistor and the output of the amplifier.
15. The amplifier of claim 1 , wherein the amplifier comprises a differential amplifier, said stages forming part of one differential circuit of a differential circuit pair.
16. The amplifier of claim 15 , wherein one of a configurable load or an LC resonator is coupled between respective outputs of each differential circuit.
17. The amplifier of claim 1 , wherein said amplifier is a low noise amplifier in a radio-frequency communications system.
18. A method for amplifying a signal comprising:
inputting the signal to an impedance matching stage;
feeding back an output of the impedance matching stage to an input of the impedance matching stage so as to provide a first, input bias voltage for the impedance matching stage;
compensating a second bias voltage for the impedance matching stage by feeding an output of the impedance matching stage through a feedback circuit comprising an amplifier circuit;
inputting the signal in parallel to a gain stage to produce a first current output;
using the output of the impedance matching stage to provide a second current output;
combining the first and second current outputs to produce a third current output; and
providing an output of the amplifier based on the third current output.
19. A method of manufacturing an amplifier comprising:
providing an impedance matching stage coupled to an input of the amplifier, including coupling an output of the impedance matching stage to provide a first, input bias voltage for the impedance matching stage;
providing a feedback circuit coupled to an output of the impedance matching stage and a voltage source, including arranging the feedback circuit to compensate a second bias voltage for the impedance matching stage;
providing a first gain stage coupled to the input of the amplifier, including arranging the output of the impedance matching stage to provide an input bias voltage for the gain stage; and
providing an output of the amplifier based on the output of the impedance matching stage and an output of the gain stage.
20. The method of manufacturing an amplifier of claim 19 , wherein:
providing the feedback circuit comprises providing an amplifier circuit to implement the feedback circuit, including coupling the output of the impedance matching stage to an inverting input of the amplifier circuit, coupling the voltage source to a non-inverting input of the amplifier circuit and setting the compensated second bias voltage for the impedance matching stage based on the output of the amplifier circuit; and
providing an output of the amplifier comprises providing a second gain stage between the output of the impedance matching circuit and the output of the amplifier such that the output of the amplifier is based on the output of the first gain stage and the output of the second gain stage.
21. The amplifier of claim 8 , further comprising:
a signal coupling stage coupled to the output of the impedance matching stage, an output of the signal coupling stage being used together with the output of the gain stage to produce the output of the amplifier,
wherein the signal coupling stage comprises a third NMOS transistor having a source, a gate and a drain, the gate of the third NMOS transistor being coupled to the output of the impedance matching stage, the source of the third NMOS transistor being coupled to the output of the gain stage.
22. The amplifier of claim 21 , wherein:
the load component comprises a PMOS transistor having a source, a gate and a drain, the gate of the PMOS transistor being coupled to the output of the feedback circuit to provide the compensated second bias voltage for the impedance matching stage, the drain of the PMOS transistor being coupled to the first node,
the output of the feedback circuit is coupled to the gate of the PMOS transistor via a first resistor and the input of the feedback circuit is coupled to the first node via a second resistor,
the gate of the PMOS transistor is coupled to the input of the amplifier via a first AC-coupling capacitor,
the gate of the third NMOS transistor is coupled to a second voltage source via a third resistor to bias the gate, the gate of the third NMOS transistor being coupled to the output of the impedance matching stage via a second AC-coupling capacitor.
23. The amplifier of claim 22 , comprising:
at least one current cascode located before the output of the amplifier, and
wherein a first one of the at least one current cascode comprises:
a fourth NMOS transistor having a source, a gate and a drain, the source of the fourth NMOS transistor being coupled to at least the output of the gain stage.
24. The amplifier of claim 23 , wherein a second one of the at least one current cascade is coupled to the first current cascode between the drain of the fourth NMOS transistor and the output of the amplifier.
25. The amplifier of claim 1 , wherein the gain stage comprises:
an NMOS transistor having a source, a gate and a drain, the gate of the NMOS transistor being coupled to the input of the amplifier, the drain of the NMOS transistor comprising the output of the gain stage.