Latency Probe
A probe within a Network-on-Chip (NoC) that can calculate a histogram of transaction data is disclosed. Some such histograms are cycles per number of pending transactions, transactions per latency, and transactions per request delay. The number of pending transactions can be measured by a register that is incremented at the start and decremented at the end of each transaction. Latencies can be measured by timers that are allocated and initialized at the start and read at the end of each transaction. Multiple counters can be used for multiple pending transactions. Multiple banks of counters can be used so that multiple transaction interfaces can complete transactions and perform histogram bin threshold comparisons simultaneously. The thresholds separating histogram bins can be programmable.
1 . A method of collecting data, in the hardware logic of a network on chip (NoC), for a histogram of a number of pending transactions comprising:
incrementing a pending transaction value when a transaction is requested;
decrementing the pending transaction value when a transaction receives a response; and
at a determined clock cycle, incrementing a first bin counter corresponding to the pending transaction value.
2 . The method of claim 1 in which the determined clock cycle is a clock cycle during which at least one transaction is pending.
3 . The method of claim 1 further comprising: programming which of the first bin counter and a second bin counter corresponds to the pending transaction value.
4 . A method of collecting data, in the hardware logic of a network on chip (NoC), for a histogram of transaction latency comprising:
initializing a first running timer at the beginning of a transaction; and
at the end of the transaction, incrementing a first bin counter corresponding to a time of the first running timer.
5 . The method of claim 4 wherein the beginning of the transaction is when the NoC receives a request.
6 . The method of claim 4 wherein the beginning of the transaction is when the NoC accepts a request.
7 . The method of claim 4 wherein the end of a transaction is when the NoC offers a response.
8 . The method of claim 4 wherein the end of a transaction is when the NoC completes a response.
9 . The method of claim 4 wherein the end of a transaction is when the NoC accepts a request.
10 . The method of claim 4 further comprising: acting on the transaction only if the transaction meets at least one filter criterion.
11 . The method of claim 10 further comprising: programming at least one filter criterion.
12 . The method of claim 4 further comprising: programming which of the first bin counter and a second bin counter corresponds to the time.
13 . The method of claim 4 further comprising the step of selecting between the first running timer and a second running timer.
14 . The method of claim 13 further comprising the step of selecting between a first bank of timers and a second bank of timers.
15 . An apparatus in the hardware logic of a network on chip (NoC) for collecting data for a histogram comprising:
an enumeration register that stores a value representing a number of pending transactions;
logic to increment or decrement the enumeration register;
at least two bin count registers;
logic to compare the value of the enumeration register to at least one threshold; and
logic to increment a selected bin count register.
16 . The apparatus of claim 15 further comprising logic to indicate when to increment the selected bin counter.
17 . The apparatus of claim 16 wherein the at least one threshold is programmable.
18 . An apparatus in the hardware logic of a network on chip (NoC) for collecting data for a histogram comprising:
at least one timer that stores a value representing a number of cycles of a pending transaction;
logic to increment the timer;
logic to initialize the timer when a go is signaled at least two bin count registers;
logic to compare the value of the timer to at least one threshold value; and
logic to increment at least one bin count register when a stop is signaled.
19 . The apparatus of claim 18 wherein the timer is dynamically allocated at the start of the transaction to that transaction within a set of a plurality of timers
20 . The apparatus of claim 18 wherein go is signaled when the NoC receives a transaction request.
21 . The apparatus of claim 18 wherein go is signaled when the NoC grants a transaction request.
22 . The apparatus of claim 18 wherein stop is signaled when the NoC offers a response.
23 . The apparatus of claim 18 wherein stop is signaled when the NoC completes a response.
24 . The apparatus of claim 18 wherein stop is signaled when the NoC grants a transaction request.
25 . The apparatus of claim 18 further comprising a filter for transactions that meet at least one criterion.
26 . The apparatus of claim 25 wherein the at least one criterion is programmable.
27 . The apparatus of claim 18 wherein the threshold value is programmable.
28 . The apparatus of claim 18 comprising a multiplicity of timer banks wherein each bank can simultaneously provide a timer value to compare to the at least one threshold value.
29 . The apparatus of claim 28 wherein a first bank is connected to a first transaction interface of the NoC and a second bank is connected to a second transaction interface of the NoC.
30 . The apparatus of claim 29 further comprising logic to switch the connection of transaction interfaces to banks.
31 . The apparatus of claim 15 or claim 18 further comprising clock domain crossing logic between at least one network interface unit (NIU) and the histogram bin counters.
32 . The apparatus of claim 15 or claim 18 further comprising a transaction filter.