Network processor
View Patent ↗The present invention discloses a network processor for a broadband gateway. The network processor includes a host processor; a plurality of networking interfaces, corresponding to a plurality of networking technologies, respectively; and a network address translation (NAT) engine, for accelerating packet processing from a first networking interface to a second networking interface.
1. A network processor for a broadband gateway, comprising:
a host processor;
a plurality of networking interfaces corresponding to a plurality of networking technologies, respectively;
a network address translation (NAT) engine, for accelerating packet processing from a first networking interface to a second networking interface; wherein the NAT engine offloads partial packet processing of the host processor for a packet from the first networking interface to the second networking interface, and the host processor performs forwarding and buffer management for the packet processed by NAT engine; and
a switch fabric, for routing the packet processed by NAT engine to store the processed packet into a memory when a data rate corresponding to the first networking interface is greater than that of the second networking interface, wherein the memory is not in the processor.
2. The network processor of claim 1 , further comprising: the NAT engine accelerates packet processing from a first local area network (LAN) domain via an Ethernet interface to a second LAN domain via the Ethernet interface.
3. The network processor of claim 2 , wherein the NAT engine offloads all packet processing of the host processor.
4. The network processor of claim 1 , further comprising: the NAT engine accelerates packet processing from a broadband internet via an Asynchronous Transfer Mode (ATM) Segmentation and Reassembly (SAR) interface to a LAN domain via an Ethernet interface.
5. The network processor of claim 4 , wherein the NAT engine offloads all packet processing of the host processor.
6. The network processor of claim 1 , wherein the NAT engine accelerates packet processing from a LAN domain via an Ethernet interface to a broadband internet via an ATM SAR interface.
7. The network processor of claim 6 , wherein the NAT engine offloads processing of classification, modification, egress port lookup and QoS statistic of the host processor.
8. The network processor of claim 7 , wherein packets are stored in a Dynamic Random Access Memory (DRAM) before the host processor forwards the packets to the ATM SAR interface.
9. The network processor of claim 1 , wherein the NAT engine accelerates packet processing from a LAN domain via an Ethernet interface to a 3G/3.5G network via a Universal Serial Bus (USB) host interface.
10. The network processor of claim 9 , wherein the NAT engine offloads processing of classification, modification, egress port lookup and QoS statistic of the host processor.
11. The network processor of claim 10 , wherein the host processor transforms packets between USB packets and internet access data.
12. The network processor of claim 1 , further comprising: the NAT engine accelerates packet processing from a broadband internet via an ATM SAR interface to a wireless local area network (WLAN) network via a Peripheral Component Interconnect Express (PCIe) interface.
13. The network processor of claim 12 , wherein the NAT engine offloads processing of classification, modification, egress port lookup and QoS statistic of the host processor.
14. The network processor of claim 13 , wherein the host processor transforms packets from internet access data into PCIe packets.
15. The network processor of claim 1 , wherein the NAT engine accelerates packet processing from a WLAN network via a PCIe interface to a broadband internet via an ATM SAR interface.
16. The network processor of claim 15 , wherein the NAT engine offloads processing of classification, modification, egress port lookup and QoS statistic of the host processor.
17. The network processor of claim 16 , wherein the host processor transforms packets from PCIe packets into internet access data, and packets are stored in a DRAM before the host processor forwards the packets to the ATM SAR interface.
18. The network processor of claim 1 further comprising a crypto engine, for offloading encryption processing of the host processor when the packets are received from the first networking interface and are transmitted to the second networking interface.
19. The network processor of claim 1 , wherein the switch fabric, for performing layer-2 packet processing.