Virtual data loopback and/or data capture in a computing system

1. A method for providing virtual data loopback in a computing system including a first instruction executing device, a second instruction executing device, and multiple interfaces for connecting the computing system with an external computing system, the method comprising:

forwarding a data packet from the first instruction executing device to the second instruction executing device;

the second instruction executing device identifying egress interface information from the data packet, the egress interface information indicating a first interface for forwarding the data packet out of the computing system;

based on the identified egress interface information indicating the first interface, the second instruction executing device automatically determining a second interface corresponding to the first interface;

the second instruction executing device inserting into the data packet ingress interface information that indicates the determined second interface;

the second instruction executing device forwarding the data packet, including the ingress interface information, back to the first instruction executing device; and

the first instruction executing device identifying from the data packet the ingress interface information that indicates the determined second interface;

such that the data packet is looped back to the first instruction executing device without being communicated via the first or second interface, and such that from the perspective of the first instruction executing device the data packet was received via the second interface;

wherein the first instruction executing device and the second instruction executing device each comprise at least one of a processor or a configurable logic device.

2. The method of claim 1 , wherein the first instruction executing device comprises a processor and the second instruction executing device comprises a configurable logic device.

3. The method of claim 2 , wherein the configurable logic device comprises a field programmable gate array (FPGA).

4. The method of claim 1 , wherein the first instruction executing device comprises a first configurable logic device and the second instruction executing device comprises a second configurable logic device.

5. The method of claim 4 , wherein the first instruction executing device comprises a first FPGA and the second instruction executing device comprises a second FPGA.

6. The method of claim 1 , wherein the second instruction executing device determines the second interface corresponding to the first interface using a lookup table that links particular ones of the multiple interfaces to each other.

7. The method of claim 1 , further comprising, before forwarding the data packet back to the first instruction executing device, the second instruction executing device:

determines whether to capture the data packet based on data capture instructions; and

if it is determined to capture the data packet, the second instruction executing device storing a copy of the data packet in a memory device coupled to the second instruction executing device.

8. A computing system, comprising:

a first instruction executing device;

a second instruction executing device; and

multiple interfaces for connecting the computing system with an external computing system;

wherein the second instruction executing device is programmed to:

receive a data packet forwarded from the first instruction executing device;

identify egress interface information from the data packet, the egress interface information indicating a first interface for forwarding the data packet out of the computing system;

based on the identified egress interface information indicating the first interface, automatically determine a second interface corresponding to the first interface;

insert into the data packet ingress interface information that indicates the determined second interface; and

forward the data packet, including the ingress interface information, back to the first instruction executing device; and

wherein the first instruction executing device is programmed to identify from the data packet the ingress interface information that indicates the determined second interface;

such that the data packet is looped back to the first instruction executing device without being communicated via the first or second interface, and such that from the perspective of the first instruction executing device the data packet was received via the second interface;

wherein the first instruction executing device and the second instruction executing device each comprise at least one of a processor or a configurable logic device.

9. The system of claim 8 , wherein the first instruction executing device comprises a processor and the second instruction executing device comprises a configurable logic device.

10. The system of claim 9 , wherein the configurable logic device comprises a field programmable gate array (FPGA).

11. The system of claim 8 , wherein the first instruction executing device comprises a first configurable logic device and the second instruction executing device comprises a second configurable logic device.

12. The system of claim 11 , wherein the first instruction executing device comprises a first FPGA and the second instruction executing device comprises a second FPGA.

13. The system of claim 8 , wherein the second instruction executing device is programmed to determine the second interface corresponding to the first interface using a lookup table that links particular ones of the multiple interfaces to each other.

14. The system of claim 8 , wherein the second instruction executing device is further programmed to, before forwarding the data packet back to the first instruction executing device:

determine whether to capture the data packet based on data capture instructions; and

if it is determined to capture the data packet, the second instruction executing device store a copy of the data packet in a memory device coupled to the second instruction executing device.