Semiconductor device
View Patent ↗An ESD protection element is disclosed in which LOCOS oxide films are formed at both ends of a gate electrode, and a conductivity type of a diffusion layer formed below one of the LOCOS oxide films which is not located on a drain side is set to a p-type, to thereby limit an amount of a current flowing in a portion below a source-side n-type high concentration diffusion layer, the current being generated due to surface breakdown of a drain. With this structure, even in a case of protecting a high withstanding voltage element, it is possible to maintain an off-state during a steady state, while operating, upon application of a surge or noise to a semiconductor device, so as not to reach a breakage of an internal element, discharging a generated large current, and then returning to the off-state again.
1. A semiconductor device, comprising:
a gate insulating film formed on a surface of a p-type semiconductor region;
a gate electrode disposed on the gate insulating film;
LOCOS oxide films disposed on portions of the surface of the p-type semiconductor region, the portions being located at both ends of the gate electrode;
a p-type channel stop diffusion layer disposed below one of the LOCOS oxide films;
a p-type high concentration diffusion layer disposed on the p-type semiconductor region so as to contact the p-type channel stop diffusion layer;
a first n-type high concentration diffusion layer disposed on the p-type semiconductor region so as to contact the p-type high concentration diffusion layer, wherein the first n-type high concentration diffusion layer is surrounded by the p-type high concentration diffusion layer in a planar manner;
an n-type channel stop diffusion layer disposed below another one of the LOCOS oxide films; and
a second n-type high concentration diffusion layer disposed to be in contact with the n-type channel stop diffusion layer.
2. The semiconductor device according to claim 1 , further comprising an n-type well diffusion layer disposed around the second n-type high concentration diffusion layer adjacent to the n-type channel stop diffusion layer.
3. The semiconductor device according to claim 1 , wherein the p-type high concentration diffusion layer, the first n-type high concentration diffusion layer, and the gate electrode are electrically connected to one another.
4. The semiconductor device according to claim 1 , wherein:
the p-type high concentration diffusion layer, the first n-type high concentration diffusion layer, and the gate electrode are connected to a potential Vss; and
the second n-type high concentration diffusion layer is connected to a power supply terminal Vdd.
5. The semiconductor device according to claim 1 , wherein:
the p-type high concentration diffusion layer, the first n-type high concentration diffusion layer, and the gate electrode are connected to a potential Vss; and
the second n-type high concentration diffusion layer is connected to an input/output terminal.
6. The semiconductor device according to claim 1 , wherein:
the p-type high concentration diffusion layer, the first n-type high concentration diffusion layer, and the gate electrode are connected to an input/output terminal; and
the second n-type high concentration diffusion layer is connected to a power supply terminal Vdd.
7. The semiconductor device according to claim 1 , wherein the first n-type high concentration diffusion layer is disposed in contact with the p-type channel stop diffusion layer, and
wherein the first n-type high concentration diffusion layer is disposed in contact with the p-type channel stop diffusion layer solely along one of relatively long sides of the first n-type high concentration diffusion layer, said one of the relatively long sides thereof being opposite to the gate electrode and surrounded partly by the p-type high concentration diffusion layer such that another of the relatively long sides and relatively short sides of the n-type high concentration diffusion layer are disposed in contact with the p-type high concentration diffusion layer.
8. The semiconductor device according to claim 7 , wherein the p-type high concentration diffusion layer is extended towards the gate electrode over said one of the relatively long sides of the first n-type high concentration diffusion layer.