JTAG-based programming and debug

1. A method of sending programming and debug commands, comprising:

providing a card including a processor, a programmable device, a plurality of configurable logic devices (CLDs) within a first debug connection chain, and a plurality of non-CLD devices within a second debug connection chain;

loading control instructions on the processor from an attached tangible, non-transitory computer-readable medium;

copying contents of a program image file by the processor from the attached tangible, non-transitory computer-readable medium across a bus to the programmable device on the card with the processor;

signaling the programmable device to send instructions to at least one CLD within the plurality of CLDs on the card with the processor;

using the programmable device to select the first debug connection chain; and

sending the instructions from the programmable device to the at least one CLD through the first debug connection chain without using the second debug connection chain.

2. The method of claim 1 , wherein the instructions comprise programming instructions within a configuration image file, the method further comprising:

copying contents of the configuration image file from the attached tangible, non-transitory computer-readable medium to the programmable device via the bus; and

copying the contents of the configuration image file to the at least one CLD via the first debug connection chain.

3. The method of claim 2 , wherein contents of the configuration image file are repeated through a second CLD positioned between the programmable device and the at least one CLD on the first debug connection chain.

4. The method of claim 1 , wherein the bus is a universal serial bus (USB).

5. The method of claim 1 , wherein the first debug connection chain comprises electrical connections including mode select connections, clock connections, and data connections.

6. The method of claim 1 , wherein the instructions are debug instructions.

7. A tangible, non-transitory computer-readable media comprising instructions that, when executed on a processor, enable the processor to perform the steps comprising:

load control instructions on a processor from an attached tangible, non-transitory computer-readable medium, the processor being on a card also including a programmable device, a plurality of configurable logic devices (CLDs) within a first debug connection chain, and a plurality of non-CLD devices within a second debug connection chain;

copy contents of a program image file by the processor from the attached tangible, non-transitory computer-readable medium across a bus to the programmable device;

signal the programmable device to select the first debug connection chain and to send instructions to at least one CLD within the plurality of CLDs through the first debug connection chain without using the second debug connection chain; and

copy contents of a configuration image file including the instructions for the at least one CLD from the attached tangible, non-transitory computer-readable medium to the programmable device via the bus.

8. The media of claim 7 , further comprising instructions in the program image file that when executed by the programmable device enable the programmable device to perform the steps comprising:

select the first debug connection chain; and

copy contents of the configuration image file to the at least one CLD via the first debug connection chain.

9. The media of claim 8 , wherein contents of the configuration image file are repeated through a second CLD positioned between the programmable device and the at least one CLD on the first debug connection chain.

10. The media of claim 7 , wherein the bus is a universal serial bus (USB).

11. The media of claim 7 , wherein the first debug connection chain comprises electrical connections including mode select connections, clock connections, and data connections.

12. The media of claim 7 , wherein the at least on CLD comprises a field programmable gate array, and wherein the instructions are designed to configure the field programmable gate array.

13. A computing system comprising a processor programmed to perform the steps comprising:

load control instructions on a processor from an attached tangible, non-transitory computer-readable medium, wherein the processor is mounted to a card, the card also including a programmable device, a plurality of configurable logic devices (CLDs) within a first debug connection chain, and a plurality of non-CLD devices within a second debug connection chain;

copy contents of a program image file by the processor from the attached tangible, non-transitory computer-readable medium across a bus to the programmable device;

signal the programmable device to select the first debug connection chain and to send instructions to at least one CLD within the plurality of CLDs through the first debug connection chain without using the second debug connection chain; and

copy contents of a configuration image file including the instructions for the at least one CLD from the attached tangible, non-transitory computer-readable medium to the programmable device via the bus.

14. The system of claim 13 , wherein the programmable device is programmed to perform the steps comprising:

select the first debug connection chain; and

copy contents of the configuration image file to the at least one CLD via the first debug connection chain.

15. The system of claim 14 , wherein contents of the configuration image file are repeated through a second CLD positioned between the programmable device and the at least one CLD on the first debug connection chain.

16. The system of claim 13 , wherein the bus is a universal serial bus (USB).

17. The system of claim 13 , wherein the first debug connection chain comprises electrical connections including mode select connections, clock connections, and data connections.

18. The system of claim 13 , wherein the plurality of CLDs comprise field programmable gate arrays.