Managing the capture of packets in a computing system

1. A method for managing the capture of packets in a computing system, the method comprising:

maintaining a buffer tail pointer in a memory of an instruction executing device;

receiving a series of packets at the instruction executing device;

for each received packet:

prepending a header comprising a packet length and a packet pointer set to a current value of the buffer tail pointer;

determining a next free memory location by adding the current value of the buffer tail pointer to the length of a previous packet identified by the buffer tail pointer;

temporarily writing the packet and prepend header to the next free memory location in a circular packet buffer in a memory coupled to the instruction executing device; and

setting the buffer tail pointer to the next free memory location; and

upon receipt by the instruction executing device of a command to generate a packet capture file:

creating a forward linked list by a process including, for each packet in the circular buffer:

extracting from the prepend header of that packet the packet pointer to a previously stored packet; and

overwriting the packet pointer to reference a subsequently stored packet; and

storing the forward linked list in the packet capture file.

2. The method of claim 1 , wherein the instruction executing device is a configurable logic device.

3. The method of claim 1 , wherein the instruction executing device is a field programmable gate array (FPGA).

4. The method of claim 1 , wherein the received packets comprise ingress packets and egress packets.

5. The method of claim 4 , wherein ingress packets are linked separately from egress packets.

6. The method of claim 5 , wherein at least one additional pointer is used to separately link ingress and egress packets.

7. The method of claim 5 , wherein the prepend header further comprises a thread type configured to indicate whether the packet is an ingress packet or an egress packet.

8. A tangible, non-transitory computer-readable media comprising a configuration file that when loaded by a configurable logic device (CLD) configures the CLD to:

maintain a buffer tail pointer in a memory of the CLD;

receive a series of packets at the CLD;

for each received packet:

prepend a header comprising a packet length and a packet pointer set to a current value of the buffer tail pointer;

determine a next free memory location by adding the current value of the buffer tail pointer to the length of a previous packet identified by the buffer tail pointer;

temporarily write the packet and prepend header to the next free memory location in a circular packet buffer in a memory coupled to the CLD; and

set the buffer tail pointer to the next free memory location; and

upon receipt by the CLD of a command to generate a packet capture file:

create a forward linked list by a process including, for each packet in the circular buffer:

extract from the prepend header of that packet the packet pointer to a previously stored packet; and

overwrite the packet pointer to reference a subsequently stored packet; and

store the forward linked list in the packet capture file.

9. The media of claim 8 , wherein the CLD is a field programmable gate array (FPGA).

10. The media of claim 8 , wherein the received packets comprise ingress packets and egress packets.

11. The media of claim 10 , wherein ingress packets are linked separately from egress packets.

12. The media of claim 11 , wherein at least one additional pointer is used to separately link ingress and egress packets.

13. The media of claim 10 , wherein the prepend header further comprises a thread type configured to indicate whether the packet is an ingress packet or an egress packet.

14. A computing system comprising:

a configurable logic device (CLD) configured to:

maintain a buffer tail pointer in a memory of the CLD;

receive a series of packets at the CLD;

for each received packet:

prepend a header comprising a packet length and a packet pointer set to a current value of the buffer tail pointer;

determine a next free memory location by adding the current value of the buffer tail pointer to the length of a previous packet identified by the buffer tail pointer;

temporarily write the packet and prepend header to the next free memory location in a circular packet buffer in a memory coupled to the CLD; and

set the buffer tail pointer to the next free memory location; and

upon receipt by the CLD of a command to generate a packet capture file:

create a forward linked list by a process including, for each packet in the circular buffer:

extract from the prepend header of that packet the packet pointer to a previously stored packet; and

overwrite the packet pointer to reference a subsequently stored packet; and

store the forward linked list in the packet capture file.

15. The system of claim 14 , wherein the CLD is a field programmable gate array (FPGA).

16. The system of claim 14 , wherein the received packets comprise ingress packets and egress packets.

17. The system of claim 16 , wherein ingress packets are linked separately from egress packets.

18. The system of claim 17 , wherein at least one additional pointer is used to separately link ingress and egress packets.

19. The system of claim 16 , wherein the prepend header further comprises a thread type configured to indicate whether the packet is an ingress packet or an egress packet.