Semiconductor device including multi-chip
View Patent ↗In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.
1. A storage device comprising:
a first semiconductor chip including a memory controller;
a second semiconductor chip configured to be connected to the first semiconductor chip, including a plurality of dynamic type memory cells which is accessed only by the memory controller;
a third semiconductor chip configured to be connected to the first semiconductor chip, including a plurality of non-volatile memory cells;
first signal lines connected between the first semiconductor chip and the second semiconductor chip and transmitting data read from and written into the plurality of dynamic type memory cells; and
second signal lines, which are separated from the first signal lines, connected between the first and third semiconductor chips and transmitting data read from and written into the plurality of non-volatile memory cells.
2. The storage device according to claim 1 ,
wherein the plurality of dynamic type memory cells includes synchronous dynamic random access memory cells operative in synchronism with a clock provided by the first semiconductor chip.
3. The storage device according to claim 1 ,
wherein the memory controller includes a refresh counter generating an address for refreshing the plurality of dynamic type memory cells.
4. The storage device according to claim 3 ,
wherein the memory controller includes a temperature measuring module detecting a temperature to adjust a refresh interval of the plurality of dynamic type memory cells.
5. The storage device according to claim 1 , wherein the memory controller comprises:
a command generator generating a command signal provided for the second semiconductor chip, the command signal including a row address strobe signal, a column address strobe signal and a write enable signal, and
an access controller generating an address signal provided for the second semiconductor chip.
6. The storage device according to claim 1 , wherein the plurality of non-volatile memory cells are flash memory cells.