Methods and apparatuses for dynamic memory termination
Described herein are a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory input-output (I/O) interface of a memory in response to a termination signal level. The method comprises: setting a first termination impedance value setting for a termination unit of an input-output (I/O) interface of a memory; assigning the first termination impedance value setting to the termination unit when the memory is not being accessed; and switching from the first termination impedance value setting to a second termination impedance value setting in response to a termination signal level.
1. A system comprising:
a synchronous dynamic random access memory (SDRAM) device, the SDRAM device comprising at least
a memory array,
a mode register to hold at least one mode register bit, wherein the value of the at least one mode register bit is to determine an on-die termination (ODT) mode based on whether the SDRAM device is selected for memory access or non-selected for memory access, and
ODT circuitry coupled with the mode register to provide a programmable termination value based on the ODT mode in accordance with a state table separate from the mode register, wherein the programmable termination value corresponds to RTT PARK to identify a finite termination value for the SDRAM device when it is non-selected for memory access, and ODT is not enabled for the SDRAM device; and
a memory controller coupled with the SDRAM device, the memory controller comprising at least command and control logic to control the ODT mode of the SDRAM and to control selection of the SDRAM device for memory access.
2. The system of claim 1 wherein the SDRAM device conforms to a Double Data Rate 4 (DDR4) specification.
3. The system of claim 2 , wherein the ODT circuitry provides programmable termination when the ODT mode is one of RTT_PARK, RTT_WR and RTT_NOM.
4. The system of claim 1 wherein the SDRAM device conforms to a Low Power Double Data Rate 4 (LPDDR4) specification.
5. The system of claim 1 wherein the ODT circuitry provides VDDQ termination.
6. The system of claim 1 wherein the ODT circuitry is to transition the ODT value from a first programmable value to a second programmable value.
7. A synchronous dynamic random access memory (SDRAM) device comprising:
a memory array,
a mode register to hold at least one mode register bit, wherein the value of the at least one mode register bit is to determine an on-die termination (ODT) mode based on whether the SDRAM device is selected for memory access or non-selected for memory access, and
ODT circuitry coupled with the mode register to provide a programmable termination value based on the ODT mode in accordance with a state table separate from the mode register by an associated memory controller that controls selection of the SDRAM device and controls the ODT mode of the SDRAM, wherein the programmable termination value corresponds to RTT PARK to identify a finite termination value for the SDRAM device when it is non-selected for memory access, and ODT is not enabled for the SDRAM device.
8. The SDRAM device of claim 7 wherein the SDRAM device conforms to a Double Data Rate 4 (DDR4) specification.
9. The SDRAM device of claim 7 wherein the SDRAM device conforms to a Low Power Double Data Rate 4 (LPDDR4) specification.
10. The SDRAM device of claim 9 , wherein the ODT circuitry provides programmable termination when the ODT mode is one of RTT_PARK, RTT_WR and RTT_NOM.
11. The SDRAM device of claim 7 wherein the ODT circuitry provides VDDQ termination.
12. The SDRAM device of claim 7 wherein the ODT circuitry is to transition the ODT value from a first programmable value to a second programmable value.
13. A memory controller comprising:
command and control circuitry to control memory access to a memory device, including controlling whether the memory device is selected for memory access or non-selected for memory access;
command and control circuitry to control an on-die termination (ODT) mode of the memory device; and
I/O (input/output) connectors to couple to the memory device over multiple signals lines, wherein the memory device includes ODT circuitry to terminate the signal lines, wherein the memory controller is to set a value of a mode register of the memory device to program a termination value to be used by the ODT circuitry via one or more commands send via the I/O connectors to the memory device, wherein the ODT modes have separately programmable termination values depending on whether the memory device is selected for memory access or non-selected for memory access and depending on a value set in a state table separate from the mode register for the respective ODT modes, wherein the programmable termination value corresponds to RTT PARK to identify a finite termination value for the SDRAM device when it is non-selected for memory access, and ODT is not enabled for the SDRAM device.
14. The memory controller of claim 13 , wherein the ODT circuitry provides programmable termination when the ODT mode is one of RTT_PARK, RTT_WR and RTT_NOM.
15. The memory controller of claim 13 wherein the ODT circuitry provides VDDQ termination.
16. The memory controller of claim 13 wherein the memory controller is contained within a single integrated circuit with at least one processor core.
17. The memory controller of claim 13 wherein the ODT circuitry is to transition the ODT value from a first programmable value to a second programmable value.