IP Library Granted Patent US 8,319,533
Granted Patent B2
US 8,319,533 · App. 13/533,661 · Granted Nov 27, 2012

System for detecting a reset condition in an electronic circuit

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Quick Facts
Patent No.
US 8,319,533
App. No.
13/533,661
Granted
Nov 27, 2012
Kind
B2
Abstract

There is disclosed a system for detecting the assertion of a reset signal. A plurality of circuit elements is configurable by a reset signal to output a string of data values in a predetermined pattern. A comparator receives the string of data values and determines whether the string of data values matches the predetermined pattern. If so, the comparator generates an output signal indicative of a reset. In one embodiment, the output signal of the comparator can be used to automatically trigger a reset if the reset signal has not been asserted.

Claims (9)

1. A system for generating a reset signal on a computing device, said system comprising:

a plurality of circuit elements including:

an input for receiving a reset signal of said computing device and,

an output for outputting a string of data values, wherein said plurality of circuit elements output a predetermined pattern of data values when said reset signal is received and output an arbitrary pattern of data values upon power up of said computing device when said reset signal has not been received;

a comparator including an input for receiving said string of data values, said comparator determining whether said string of data values matches said predetermined pattern of data values, wherein said comparator outputs a reset signal for said computing device when said string of data values fail to match said predetermined pattern of data values.

2. The system of claim 1 wherein when said comparator determines said sting of data values matches said predetermined pattern, said comparator outputs a confirmatory indicative of a reset.

3. The system of claim 1 wherein said comparator comprises a single logic gate for receiving said sting of data values at said input and producing said reset signal.

4. The system of claim 1 wherein said plurality of circuit elements comprises flip flops.

5. The system of claim 1 wherein said system is within an integrated circuit of said computing device and said reset signal provides a system-wide reset of said integrated circuit.

Assignments (4)
NUNC PRO TUNC ASSIGNMENT Recorded Jun 19, 2023
From: BLACKBERRY LIMITED
To: MALIKIE INNOVATIONS LIMITED
Reel/Frame 064270/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2023
From: BLACKBERRY LIMITED
To: MALIKIE INNOVATIONS LIMITED
Reel/Frame 064104/0103 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 2, 2019
From: CERTICOM CORP.
To: BLACKBERRY LIMITED
Reel/Frame 050610/0937 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 29, 2012
From: FULLER, JAY SCOTT
To: CERTICOM CORP.
Reel/Frame 028467/0469 →