Latency adjustment based on stack position identifier in memory devices configured for stacked arrangements
View Patent ↗Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.
1. A semiconductor memory device, comprising:
a stack position identifier configured to identify a position of the semiconductor memory device in an aligned vertical stack of a plurality of semiconductor memory devices, wherein the plurality of semiconductor devices are coupled together via a common vertical connection;
a latency determiner configured to determine a programmed latency from a mode register on the semiconductor memory device; and
a latency adjustor configured to:
determine a predetermined latency adjustment based on the stack position identifier; and
add the predetermined latency adjustment to the programmed latency to thereby adjust the programmed latency in response to the stack position identifier.
2. The semiconductor memory device of claim 1 , wherein the common vertical connection comprises a DQ signal.
3. The semiconductor memory device of claim 1 , wherein the latency adjustor is configured to adjust the programmed latency in response to an enable signal, and wherein the enable signal is active.
4. The semiconductor memory device of claim 1 , wherein the latency adjustor is configured to not adjust the programmed latency in response to an enable signal, and wherein the enable signal is inactive.
5. The semiconductor memory device of claim 1 , wherein the common vertical connection comprises a through-silicon via (TSV).
6. The semiconductor memory device of claim 1 , wherein the common vertical connection comprises a die-to-die via.
7. The semiconductor memory device of claim 1 , wherein the programmed latency comprises at least one of a read latency, a column access strobe (CAS) latency, an additive latency, and a CAS write latency.
8. A method of adjusting a latency in a semiconductor memory device, the method comprising:
identifying a position of the semiconductor memory device in an aligned vertical stack of a plurality of semiconductor memory devices, wherein the plurality of semiconductor devices are coupled together via a common vertical connection;
determining a programmed latency from a mode register on the semiconductor memory device;
determining a predetermined latency adjustment based on the stack position identifier; and
adjusting the programmed latency in response to the stack position identifier by adding the predetermined latency adjustment to the programmed latency.
9. The method of claim 8 , wherein the adjusting the programmed latency is performed in response to an enable signal being active.
10. The method of claim 8 , wherein the common vertical connection comprises a through-silicon via (TSV).
11. The method of claim 8 , wherein the common vertical connection comprises a die-to-die via.
12. An apparatus having an aligned vertical stack of a plurality of semiconductor memory devices, the apparatus comprising for a semiconductor memory device:
a stack position identifier configured to identify a position of the semiconductor memory device in the aligned vertical stack of the plurality of semiconductor memory devices, wherein the plurality of semiconductor devices are coupled together via a common vertical connection;
a latency determiner configured to determine a programmed latency from a mode register on the semiconductor memory device; and
a latency adjustor configured to:
determine a predetermined latency adjustment based on the stack position identifier; and
add the predetermined latency adjustment to the programmed latency to thereby adjust the programmed latency in response to the stack position identifier.
13. The apparatus of claim 12 , the common vertical connection comprises a through-silicon via (TSV).
14. The apparatus of claim 12 , wherein the common vertical connection comprises a DQ signal.