IP Library Granted Patent US 8,762,900
Granted Patent B2
US 8,762,900 · App. 13/534,765 · Granted Jun 24, 2014

Method for proximity correction

Inventors: Jaw-Jung Shin (Hsinchu, TW); Shy-Jay Lin (Jhudong Township, Hsinchu County, TW); Hua-Tai Lin (Hsinchu, TW); Burn Jeng Lin (Hsin-Chu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,762,900
App. No.
13/534,765
Granted
Jun 24, 2014
Kind
B2
Abstract

A method of an integrated circuit (IC) design includes receiving an IC design layout. The IC design layout includes an IC feature with a first outer boundary and a first target points assigned to the first outer boundary. The method also includes generating a second outer boundary for the IC feature and moving all the first target points to the second outer boundary to form a modified IC design layout.

Claims (37)

1. A method for making a mask for an integrated circuit (IC) design, the method comprising:

receiving an IC design layout, the IC design layout including:

an IC feature with a first outer boundary, and

first target points assigned to the first outer boundary;

generating, using a computing system, a second outer boundary for the IC feature;

moving all the first target points to the second outer boundary to form a modified IC design layout; and

providing the modified IC design layout for fabrication of the mask,

wherein the second outer boundary is generated by applying convolution of the IC design layout with a predetermined function, and

wherein the predetermined function includes a Sinc function in a form of [sin 2 (x/σ)/(x/σ) 2 ]×[sin 2 (y/σ)/(y/σ) 2 ], where x and y are positions in an x direction and a y direction, respectively, and σ is a resolution blur size of an exposure system.

2. The method of claim 1 , wherein the exposure system includes a photon exposure system with a wavelength (λ).

3. The method of claim 1 , wherein the resolution blur size is calculated by (k 1 ×λ/NA), where k 1 is a constant, λ is a wavelength of a photon, and NA is a numerical aperture of the photon exposure system.

4. The method of claim 1 , wherein the second outer boundary contains one or more rounding corners.

5. The method of claim 1 , wherein the first target points are moved to the second outer boundary in a perpendicular direction to the first outer boundary.

6. The method of claim 1 , wherein after moving the first target points to the second outer boundary and forming the modified IC design layout and before providing the modified IC design layout for fabrication, the method further comprising:

performing optical proximity correction (OPC) on the modified IC design layout.

7. The method of claim 1 , wherein after moving the first target points to the second outer boundary and forming the modified IC design layout and before providing the modified IC design layout for fabrication, the method further comprising:

performing electron proximity correction (EPC) on the modified IC design layout.

8. The method of claim 1 , further comprising:

performing a photolithography simulation on the modified IC design layout; and

performing an error evaluation on the modified IC design layout.

9. A method for making a mask for an integrated circuit (IC) design layout, the method comprising:

receiving the IC design layout having an IC feature with a first outer boundary;

assigning first target points to the first outer boundary;

applying, using a computer, a convolution on the IC design layout with a predetermined function to generate a second outer boundary of the IC feature;

moving the first target points to the second outer boundary to form a modified IC design layout;

performing a proximity correction on the modified IC design layout; and

performing a photolithography simulation on the modified IC design layout, wherein the predetermined function includes a Gaussian function employed in a form of where exp[−x 2 /(2σ x 2 )−y 2 /(2σ y 2 )], where x and y are positions in an x direction and a y direction, respectively, and σ x and σ y is a resolution blur size of an exposure system in the x direction and the y direction, respectively.

10. The method of claim 9 , wherein the exposure system includes a charged-particle exposure system.

11. The method of claim 9 , wherein the second outer boundary contains one or more rounding corners.

12. A method comprising:

receiving a design layout having a feature, wherein the feature has a first boundary;

assigning a target point to the first boundary;

using a computing system, performing a photolithographic simulation on the design layout to determine a second boundary for the feature, wherein the photolithographic simulation includes performing a mathematical convolution of the design layout with an equation modeling a photolithographic blur of a photolithographic exposure system;

relocating the target point based on the second boundary of the feature; and

providing the design layout having the relocated target point for performing a proximity correction thereupon,

wherein the equation includes at least one of: a Sinc function in a form of [sin 2 (x/σ)/(x/σ) 2 ]×[sin 2 (y/σ)/(y/σ) 2 ], where x and y are positions in an x direction and a y direction, respectively, and σ is a resolution blur size of an exposure system, and a Gaussian function employed in a form of exp[−x 2 /(2σ x 2 )−y 2 /(2σ y 2 )], where x and y are positions in an x direction and a y direction, respectively, and σ x and σ y are a resolution blur size of an exposure system in the x direction and the y direction, respectively.

13. The method of claim 12 , wherein the assigning of the target point to the first boundary of the feature includes assigning a number of target points to the feature based on an error tolerance.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2012
From: SHIN, JAW-JUNG; LIN, SHY-JAY; LIN, HUA-TAI; LIN, BURN JENG
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 028985/0222 →
Continuity (1)
Related Publication 20140007023A1 · Jan 2, 2014