IP Library Granted Patent US 9,251,552
Granted Patent B2
US 9,251,552 · App. 13/536,221 · Granted Feb 2, 2016

Method and apparatus for managing image data for presentation on a display

Inventors: Seh Kwa (Saratoga, CA); Nir Sucher (Ramat Hashofet, IL); Vijay Sai Reddy Degalahal (Bangalore, IN)
Assignee: INTEL CORPORATION
G06T1/20G09G5/363G09G2330/021G09G2340/0435G09G2360/18
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Quick Facts
Patent No.
US 9,251,552
App. No.
13/536,221
Granted
Feb 2, 2016
Kind
B2
Abstract

An apparatus may include a memory and graphics logic operative to render a set of one or more data frames for storage in the memory using a received set of data of a digital medium, and output one or more control signals at a first interval. The apparatus may also include a display engine operative to receive the one or more control signals from the graphics logic, retrieve the set of one or more data frames from the memory, and send the one or more data frames to a display device for visual presentation. The one or more data frames may be sent periodically in succession at a second interval corresponding to a native frame rate of the digital medium.

Claims (43)

1. An apparatus, comprising:

a memory;

graphics logic operative to:

look ahead in a command queue to process a multiplicity of data frame;

render the multiplicity of data frames using a received set of data of a digital medium in an instance, the received set of data to comprise a frame rate;

store the multiplicity of data frames to the memory;

output a first control signal at a first interval; and

send a second control signal to one or more devices, the second control signal to include an indication to enter a low power mode for a period of time, the period of time based on the quantity of individual frames in the multiplicity of frames and the frame rate and substantially equal to the product of the quantity of individual frames in the multiplicity of frames and the frame rate; and

a display engine operative to:

receive the first control signal from the graphics logic;

retrieve the multiplicity of data frames from the memory; and

send the multiplicity of data frames to a display device for visual presentation in a single instance.

2. The apparatus of claim 1 , the one or more devices including a central processing unit (CPU), a graphics processing unit (GPU), or a voltage regulator.

3. The apparatus of claim 1 , the multiplicity of data frames comprising compressed data.

4. The apparatus of claim 1 , the display device comprising a refresh rate, the frame rate comprising 1/24 th of a second and the refresh rate less than or equal to 1/48 th of a second.

5. The apparatus of claim 1 , the control signal comprising a frame buffer flip notification in which designation of the memory is switched from a back buffer to a front buffer to be read by the display engine.

6. The apparatus of claim 1 , comprising the display device, the display device operative to present the multiplicity of data frames as a video presentation, the refresh rate comprising 48 Hz or greater.

7. A computer implemented method, comprising:

looking ahead in a command queue to process a multiplicity of data frames;

rendering the multiplicity of data frames for storage in a first memory using a received set of data of a digital medium, the received set of data to comprise a frame rate;

outputting a first control signal at a first interval;

retrieving the multiplicity of data frames from the first memory;

sending the multiplicity of data frames to a display device for visual presentation in a single instance; and

sending a second control signal to one or more devices, the second control signal to include an indication to enter a low power mode for a period of time, the period of time based on the quantity of individual frames in the multiplicity of frames and the frame rate and substantially equal to the product of the quantity of individual frames in the multiplicity of frames and the frame rate.

8. The computer implemented method of claim 7 , the one or more devices comprising a central processing unit (CPU), a graphics processing unit (GPU), or voltage regulator.

9. The computer implemented method of claim 7 , the frame rate being 1/24 th of a second.

10. At least one non-transitory computer-readable storage medium comprising instructions that, when executed, cause a system to:

look ahead in a command queue to process a multiplicity of data frames;

render the multiplicity of data frames for storage in a first memory using a received set of data of a digital medium, the received set of data to comprise a frame rate;

output a first control signal at a first interval;

retrieve the multiplicity of data frames from the first memory;

send the multiplicity of data frames to a display device for visual presentation in a single instance; and

send a second control signal to one or more devices, the second control signal to include an indication to enter a low power mode for a period of time, the period of time based on the quantity of individual frames in the multiplicity of frames and the frame rate and substantially equal to the product of the quantity of individual frames in the multiplicity of frames and the frame rate.

11. The at least one computer-readable storage medium of claim 10 , the one or more device a central processing unit (CPU), a graphics processing unit (GPU), or voltage regulator.

12. The at least one computer-readable storage medium of claim 10 , the frame rate equal 1/24 th of a second and a refresh rate of the display device less than or equal to 1/48 th of a second.

13. An apparatus, comprising:

a memory;

graphics logic operative to:

look ahead in a command queue to process a multiplicity of data frames;

render the multiplicity of data frames for storage in a first memory using a received set of data of a digital medium, the received set of data to comprise a frame rate;

output a first control signal at a first interval, the first control signal operative to direct transmission of the multiplicity of data frames to a display device for visual presentation in a single instance, a refresh rate of the display device to exceed the frame rate; and

send a second control signal to one or more devices, the second control signal to include an indication to enter a low power mode for a period of time, the period of time based on the quantity of individual frames in the multiplicity of frames and the frame rate and substantially equal to the product of the quantity of individual frames in the multiplicity of frames and the frame rate.

14. The apparatus of claim 13 , the one or more devices including a central processing unit (CPU), a graphics processing unit (GPU), or a voltage regulator.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2012
From: KWA, SEH; SUCHER, NIR; DEGALAHAL, VIJAY SAI REDDY
To: INTEL CORPORATION
Reel/Frame 028767/0048 →
Continuity (1)
Related Publication 20140002465A1 · Jan 2, 2014