IP Library Granted Patent US 8,432,170
Granted Patent B1
US 8,432,170 · App. 13/536,238 · Granted Apr 30, 2013

Integrated capacitance model circuit

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Quick Facts
Patent No.
US 8,432,170
App. No.
13/536,238
Granted
Apr 30, 2013
Kind
B1
Abstract

Apparatuses and methods of an integrated capacitance model circuit are described. A capacitance model circuit is disposed on a common carrier substrate of an integrated circuit (IC) having a capacitance-sensing device. The capacitance model circuit is configured to model a capacitance of an external sense array. The capacitance model circuit is programmable.

Claims (29)

1. An integrated circuit comprising:

a capacitance-sensing device disposed on an common carrier substrate of the integrated circuit; and

a capacitance model circuit disposed on the common carrier substrate, wherein the capacitance model circuit is configured to model a capacitance of an external sense array, and wherein the capacitance model circuit is programmable, wherein the capacitance model circuit comprises:

an input comprising a switch coupled to receive a transmit (TX) signal;

an output comprising a plurality of switches coupled to output a receive (RX) signal; and

a plurality of programmable capacitors coupled to at least one of the input or output, wherein the plurality of programmable capacitors comprises:

a first set of one or more capacitors coupled between the input and output;

a first set of one or more switches, each coupled to one of the first set of capacitors to turn on and off the corresponding capacitor;

a second set of one or more capacitors coupled between a ground potential and the output; and

a second set of one or more switches, each coupled to one of the second set of capacitors to turn on and off the corresponding capacitor.

2. The integrated circuit of claim 1 , wherein the capacitance model circuit is configured to model an intersection of electrodes of the external sense array.

3. The integrated circuit of claim 1 , wherein the capacitance model circuit comprises at least one of programmable mutual capacitance and programmable self capacitance.

4. The integrated circuit of claim 1 , wherein the capacitance-sensing device comprises:

a transmitter;

a plurality of receive channels of a capacitance-sensing circuit; and

a sequencer coupled to the capacitance model circuit, wherein the sequencer is configured to couple the transmitter to an input of the capacitance model circuit and to couple an output of the capacitance model circuit to one or more of the plurality of receive channels.

5. The integrated circuit of claim 1 , wherein the first set of one or more capacitors are coupled in parallel to one another, and wherein the second set of one or more capacitors are coupled in parallel to one another.

6. The integrated circuit of claim 1 , wherein the first set of one or more capacitors are configured to model a mutual capacitance of the external sense array.

7. The integrated circuit of claim 1 , wherein the second set of one or more capacitors are configured to model a self capacitance of the external sense array.

8. The integrated circuit of claim 1 , wherein the capacitance model circuit is configured to model both a mutual capacitance and a self capacitance of the external sense array.

9. The integrated circuit of claim 1 , wherein the external sense array is a touchscreen.

10. The integrated circuit of claim 1 , wherein the capacitance model circuit comprises a plurality of programmable capacitors.

11. The integrated circuit of claim 10 , wherein the plurality of programmable capacitors are at least one of vertical parallel plate (VPP) capacitors, metal oxide semiconductor (MOS) capacitors, or metal-insulator-metal (MIM) capacitors.

12. An integrated circuit comprising:

a capacitance-sensing circuit comprising a plurality of sensing channels; and

a capacitance model circuit comprising a plurality of programmable capacitors, wherein the capacitance model circuit is configured to model a capacitance of an external sense array to test the plurality of sensing channels of the capacitance-sensing circuit, wherein the capacitance-sensing circuit comprises:

a transmitter; and

a sequencer coupled to the capacitance model circuit, wherein the sequencer is configured to couple the transmitter to an input of the capacitance model circuit and to couple an output of the capacitance model circuit to one or more of the plurality of sensing channels.

13. The integrated circuit of claim 12 , wherein the capacitance model circuit is configured to model at least one of a mutual capacitance, a self capacitance, or a combination of both.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION
To: PARADE TECHNOLOGIES, LTD.
Reel/Frame 036508/0284 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS AND TRADEMARKS Recorded Aug 4, 2015
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT FOR THE SECURED PARTIES
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036264/0114 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
PATENT SECURITY AGREEMENT Recorded Nov 14, 2013
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 031636/0105 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2012
From: WALSH, PAUL M.; O'DONOGHUE, KEITH
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 028462/0539 →