Sequential electrostatic discharge (ESD)-protection employing cascode NMOS triggered structure
View Patent ↗An Electrostatic Discharge (ESD) protection circuitry comprises a protection device structure. The protection device structure includes at least one transistor with a gate operably connected to a pad. The at least one transistor turns on upon an ESD event and conducting charge to a substrate. At least one additional transistor with a gate operably connected to the substrate turns on after the at least one transistor upon an ESD protection event.
1. An Electrostatic Discharge (ESD) protection circuitry comprising:
a protection device structure including:
at least one transistor with a gate operably connected to a pad, the at least one transistor turning on in response to an ESD event and conducting charge to a substrate; and
at least one additional transistor with a gate operably connected to the substrate,
wherein the at least one additional transistor is configured to turn on after the at least one transistor in response to the ESD event,
wherein the at least one transistor and at least one additional transistor are operably further connected to transistors in a cascode configuration and comprising gates connected to a supply voltage.
2. The ESD protection circuitry of claim 1 , wherein the protection device structure includes multiple at least one transistors.
3. The ESD protection circuitry of claim 1 , wherein the protection device structure includes multiple at least one additional transistors.
4. The ESD protection circuitry of claim 1 , wherein the protection device structure includes more of the at least one additional transistors than the at least one transistors.
5. The ESD protection circuitry of claim 1 , further comprising additional protection device structures.
6. The ESD protection circuitry of claim 5 , wherein the protection device structure is connected to another protection device structure using a resistor.