Semiconductor device having DLL circuit and control method thereof
Disclosed herein is a device that comprises a delay line delaying a first clock signal in response to the delay control information to produce a delayed clock signal, a phase detector unit controls the delay control information in response to a relationship in phase between the first clock signal and a second clock signal, and an inverting control unit receiving the delayed clock signal and producing a third clock signal, the second clock signal being produced in response to the third clock signal. The third clock signal is in phase with the delayed clock signal when the inverting control unit is in a first state and complementary to the delayed clock signal when the inverting control unit is in a second state.
1. A device comprising:
a delay line unit supplied with delay control information, the delay line configured to delay a first clock signal in response to the delay control information to produce a delayed clock signal;
a phase detector unit supplied with the first clock signal and a second clock signal and configured to control the delay control information in response to a relationship in phase between the first and second clock signals; and
a circuit unit coupled between the delay line unit and the phase detector unit, the circuit unit including an inverting control unit configured to receive the delayed clock signal and to produce a third clock signal, the third clock signal being in phase with the delayed clock signal when the inverting control unit is in a first state and complementary to the delayed clock signal when the inverting control unit is in a second state, the circuit unit being configured to produce the second clock signal as a replica signal in response to the third clock signal.
2. The device as claimed in claim 1 , wherein the inverting control unit is in the first state when one of leading and trailing edges of the second clock signal appears during a first logic level of the first clock signal and in the second state when the one of leading and trailing edges of the second clock signal appears during a second logic level of the first clock signal.
3. The device as claimed in claim 1 , wherein the inverting control unit is supplied with an output of the phase detector unit to take one of the first and second state.
4. The device as claimed in claim 1 , further comprising a counter unit, a count value of the counter unit serving as the delay control information and being controlled by an output of the phase detector unit.
5. The device as claimed in claim 4 , wherein the counter unit is configured to take an initial value in response to an initial state so that the delay control information is changed from the initial value in response to the output of the phase detector unit.
6. A device comprising:
a counter unit configured to generate a count value;
a delay line configured to delay a first clock signal based on the count value to generate a second clock signal;
an inversion control unit configured to select one of a non-inverted signal of the second clock signal and an inverted signal of the second clock signal to output a third clock signal;
a replica output unit configured to generate a fourth clock signal based on the third clock signal;
a phase comparison unit configured to compare phases of the first and fourth clock signals to generate a phase determination signal; and
a control unit configured to generate a reset signal, an inversion control signal, a code update signal, and a counter update signal, wherein
the count value of the counter unit is initialized to a first initial value and the inversion control unit selects the non-inverted signal when the reset signal is activated,
the inversion control unit is configured to select one of the non-inverted signal and the inverted signal based on a logic level of the phase determination signal when the inversion control signal is activated,
the count value of the counter unit is updated from the first initial value to a second initial value when the code update signal is activated after the inversion control signal is activated, and
the count value of the counter unit is counted up or counted down from the second initial value based on a logic level of the phase determination signal when the counter update signal is activated.
7. The device as claimed in claim 6 , wherein a phase difference between the second clock signal in which the count value indicates the first initial value and the second clock signal in which the count value indicates the second initial value is larger than an amount of phase shift of the second clock signal when the counter update signal is activated.
8. The device as claimed in claim 6 , wherein a phase difference between the second clock signal in which the count value indicates the first initial value and the second clock signal in which the count value indicates the second initial value is larger than an amount of jitter included in the first clock signal.
9. The device as claimed in claim 6 , wherein the first initial value is offset from a central value of the count value.
10. The device as claimed in claim 9 , wherein the second initial value is offset from the central value of the count value, and an amount of offset of the second count value is smaller than an amount of offset of the first count value.
11. The device as claimed in claim 6 , wherein the second initial value is variable based on a setting signal.
12. The device as claimed in claim 11 , further comprising a non-volatile storage circuit that stores the setting signal in a non-volatile manner.
13. A method comprising:
delaying a first clock signal to produce a delayed clock signal;
producing an inverted signal of the delayed clock signal;
detecting a relationship in phase between the first clock signal and a second clock signal to produce a detection signal;
selecting one of the delayed signal and the inverted signal in response to the detection signal; and
producing the second clock signal as a replica signal in response to a selected one of the delayed signal and the inverted signal.
14. The method as claimed in claim 13 , wherein the selecting is performed such that the delayed clock signal is selected when one of leading and trailing edges of the second clock signal appears during a first logic level of the first clock signal and the inverted signal is selected when the one of leading and trailing edges of the second clock signal appears during a second logic level of the first clock signal.
15. The method as claimed in claim 14 , wherein the delaying is performed such that the first clock signal is delayed by an amount related to a count value that is controlled by the detection signal.
16. The method as claimed in claim 14 , wherein the detection signal takes a first level when the one of leading and trailing edges of the second clock signal appears during the first logic level of the first clock signal and a second level when the one of leading and trailing edges of the second clock signal appears during the second logic level of the first clock signal.