On-chip interferers for standards compliant jitter tolerance testing
View Patent ↗Systems and methods that facilitate on-chip testing are provided. An integrated circuit can include a transmitter configured to transmit a communications signal via a communications channel. The integrated circuit can also include a receiver configured to receive the communications signal via the communications channel. A jitter creation module also can form part of the integrated circuit and can introduce jitter into the system thereby allowing for on-chip jitter testing. The jitter creation module can form either part of the transmitter or receiver and can introduce the jitter by phase interpolation.
1. An integrated circuit for communicating signals with predetermined jitter, comprising:
an output queue having a signal input, a clock input and an output, wherein the output queue is configured to output a signal received at the signal input according to a clock signal received at the clock input;
a phase adjuster configured to receive a phase adjustment input signal, and generate the clock signal by shifting the phase adjustment input signal according to a received phase control signal, and output the clock signal to the clock input of the output queue;
a jitter test module configured to receive a jitter input signal and generate a jitter control signal based on the jitter input signal; and
a combiner configured to produce the phase control signal by combining the jitter control signal with a transmit control signal.
2. The integrated circuit of claim 1 , further comprising a processing module configured to generate a communication signal and output the communication signal to the signal input of the output queue.
3. The integrated circuit of claim 2 , wherein the communication signal is generated from a received input communication signal.
4. The integrated circuit of claim 3 , wherein the processing module further comprises a transmit control module configured to recover a clock signal associated with an input communication signal and output the transmit control signal based on the recovered clock signal.
5. The integrated circuit of claim 4 , wherein the transmit control module is configured to only output the transmit control signal when the circuit is operating in a loop-back mode.
6. The integrated circuit of claim 4 , wherein the received control signal for the phase adjuster is a combination of the transmit control signal and the jitter control signal.
7. The integrated circuit of claim 2 , wherein the processing module further comprises a test signal generator configured to generate a test signal based on a received test clock signal.
8. The integrated circuit of claim 7 , wherein the processing module outputs the test signal as the communication signal when the circuit is operating in a test mode.
9. The integrated circuit of claim 1 , wherein the jitter input signal is received by a user controlled interface and defines a type and severity of jitter to be added to the output signal of the output queue.
10. The integrated circuit of claim 9 , wherein the phase adjuster controls the phase of the output signal of the output queue according to the type and severity of jitter defined by the jitter input signal.
11. The integrated circuit of claim 1 , wherein the phase adjuster is a phase interpolator.
12. A method of on-chip jitter tolerance testing in an integrated circuit for communications, the method comprising:
receiving a jitter input signal at the integrated circuit;
generating a jitter control signal based on the jitter input signal;
combining the jitter control signal with a transmission control signal to create a combined signal;
generating a test signal based on a received clock signal;
generating a communications signal based on the test signal, wherein the communications signal is generated from the test signal by introducing jitter to the communications signal according to the combined signal; and
transmitting the communications signal over a communications channel.
13. The method of claim 12 , wherein the jitter input signal defines a type and severity of jitter added that is to be added to the test signal.
14. The method of claim 13 , wherein the jitter is introduced by varying a phase of the test signal during transmission.
15. The method of claim 14 , further comprising:
receiving the communications signal via the communications channel and generating an output signal based on the received communications signal,
analyzing the output signal to determine if the integrated circuit satisfies a jitter requirement.
16. The method of claim 15 , wherein receiving the communications signal via the communications channel includes introducing additional jitter according to a second jitter control signal.
17. The method of claim 12 , further comprising:
generating a combined signal by combining the jitter control signal with a transmission control signal.
18. The method of claim 12 , wherein generating the communications signal comprises generating the jitter based on the combined signal.
19. The method of claim 12 , wherein the jitter is introduced to the communications signal by modifying a phase of the communications signal during transmission using a phase adjuster.
20. The method of claim 12 , wherein transmitting the communications signal over a communications channel comprises outputting the communications signal to an output queue.