Integration methods to fabricate internal spacers for nanowire devices
A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.
1. A semiconductor device, comprising:
a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires;
a gate structure comprising a gate dielectric and a gate electrode, the gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate structure sidewalls, the gate structure having a portion above the nanowire stack;
a pair of external gate sidewall spacers adjacent to opposite gate structure sidewalls of the portion of the gate structure above the nanowire stack;
a pair of source/drain regions on opposite sides of the channel region; and
an internal insulative spacer adjacent to a portion of one of the gate sidewalls between adjacent nanowires, internal to the nanowire stack and the internal insulative spacer beneath one of the external gate sidewall spacers, the internal insulative spacer between and in direct physical contact with both of the gate dielectric and one of the source/drain regions.
2. The semiconductor device of claim 1 , further comprising bottom internal insulative spacers adjacent to the structure gate sidewalls underneath a bottom nanowire in the nanowire stack.
3. The semiconductor device of claim 1 , wherein the internal insulative spacer is formed from a dielectric material selected from the group consisting of SiN, SiO 2 , SiON, and SiC.
4. The semiconductor device of claim 1 , wherein the external spacers have a first thickness normal to the surface of the gate structure sidewalls, wherein the internal insulative spacers has a second thickness normal to the gate structure sidewalls, and wherein the second thickness is equal to the first thickness.
5. The semiconductor device of claim 1 , wherein the source/drain regions of the device comprise a source/drain portion of the nanowires.
6. The semiconductor device of claim 1 , wherein the source/drain regions of the device comprise a homogeneous semiconductor material.
7. The semiconductor device of claim 1 , wherein the substrate is an SOI substrate.
8. The semiconductor device of claim 1 , further comprising a pair of source/drain contacts in contact with the source/drain regions of the device.
9. The semiconductor device of claim 8 , wherein the internal spacer isolates one of the source/drain contacts from the portion of the one of the gate structure sidewalls internal to the nanowire stack.