IP Library Granted Patent US 9,164,771
Granted Patent B2
US 9,164,771 · App. 13/539,223 · Granted Oct 20, 2015

Method for thread reduction in a multi-thread packet processor

Inventor: Hamid Assarpour (Arlington, MA)
Assignee: AVAYA INC.
G06F9/38G06F9/30076G06F9/46
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Quick Facts
Patent No.
US 9,164,771
App. No.
13/539,223
Granted
Oct 20, 2015
Kind
B2
Abstract

Key lookup operations are broken into two instructions: a Key Dispatch Instruction (KDI), and a Return Result Instruction (RRI). The thread uses KDI to dispatch key information to a selected coprocessor to initiate a key lookup operation. Upon dispatch of the key value to the coprocessor, the KDI is retired to enable the thread to continue to dispatch and retire addition instructions in the pipeline and does not go idle. Subsequently, the thread will issue a RRI to obtain the key lookup result from the coprocessor. While a thread is executing, it maintains, as part of its context, a busy flag per coprocessor in a scoreboard register and a return result register per coprocessor. KDI causes the corresponding busy flag in the scoreboard register to be set. When the key lookup operation is complete, the busy flag is cleared and the result is stored in the return result register.

Claims (29)

1. A method of thread reduction in a multi-thread packet processor, the method comprising the steps of:

executing, by a thread in a multi-thread packet processor, a first plurality of stages of a packet processing pipeline;

dispatching, by the thread, a key dispatch instruction to a coprocessor to cause the coprocessor to initiate a key lookup operation;

executing, by the thread, a second plurality of stages of the packet processing pipeline;

issuing, by the thread, a return result instruction to obtain a result of the key lookup operation from the coprocessor;

wherein the step of executing the second plurality of stages occurs after the step of dispatching the key dispatch instruction and prior to the step of issuing the return result instruction.

2. The method of claim 1 , further comprising the steps of receiving a packet and assigning the packet to a free thread in the multi-thread packet processor.

3. The method of claim 2 , wherein each thread is assigned to a separate packet.

4. The method of claim 1 , further comprising maintaining a busy flag for the coprocessor.

5. The method of claim 4 , wherein the busy flag is set when the key dispatch instruction is dispatched to the coprocessor.

6. The method of claim 4 , wherein the busy flag is cleared when the coprocessor completes execution of the key lookup operation.

7. The method of claim 6 , wherein the return result instruction is not issued until the busy flag is cleared.

8. The method of claim 6 , wherein the coprocessor stores the result of the key lookup operation in a return result register, and wherein the return result instruction causes the result of the key lookup operation to be read from the return result register.

9. The method of claim 1 , wherein the step of executing, by the thread, the second plurality of stages of the packet processing pipeline occurs in parallel with implementation of the key lookup operation by the coprocessor.

10. A network element, comprising:

a coprocessor; and

a multi-thread packet processor, each thread configured to sequentially implement a plurality of stages of a packet processing pipeline, the plurality of stages including a first plurality of stages, a key dispatch instruction, a second plurality of stages, and a return result instruction,

wherein:

the key dispatch instruction is configured to cause the coprocessor to initiate a key lookup operation;

the return result instruction is configured to obtain a result of the key lookup operation from the coprocessor; and

the thread executes the second plurality of stages of the packet processing pipeline after implementing the key dispatch instruction to cause the coprocessor to implement the key lookup operation and prior to implementing the return result instruction to obtain the result of the key lookup operation from the coprocessor.

11. The network element of claim 10 , wherein each thread of the multi-thread packet processor is assigned to a separate packet.

12. The network element of claim 10 , further comprising multiple coprocessors and a scoreboard table maintaining a set of flags, each flag being associated with one of the coprocessors.

13. The network element of claim 12 , wherein a busy flag for a respective one of the coprocessors is set in the scoreboard table when the key dispatch instruction is implemented to cause the respective one of the coprocessors to implement the key lookup operation.

14. The network element of claim 13 , wherein the busy flag for the respective one of the coprocessors is cleared in the scoreboard table when the respective one of the coprocessors completes execution of the key lookup operation.

15. The network element of claim 14 , wherein the return result instruction is not issued until the busy flag is cleared.

16. The network element of claim 14 , further comprising a set of return result registers, each of the result registers being associated with a corresponding one of the plurality of coprocessors.

17. The network element of claim 14 , wherein the respective coprocessor stores the result of the key lookup operation in its associated return result register, and wherein the return result instruction causes the result of the key lookup operation to be read from the return result register of the respective coprocessor.

18. The network element of claim 10 , wherein the network element is configured such that execution of the second plurality of stages of the packet processing pipeline occurs in parallel with implementation of the key lookup operation by the coprocessor.

Assignments (13)
AMENDED SECURITY AGREEMENT Recorded Aug 18, 2023
From: EXTREME NETWORKS, INC.; AEROHIVE NETWORKS, INC.
To: BANK OF MONTREAL
Reel/Frame 064782/0971 →
SECURITY INTEREST Recorded May 1, 2018
From: EXTREME NETWORKS, INC.
To: BANK OF MONTREAL
Reel/Frame 046050/0546 →
RELEASE OF SECURITY INTEREST Recorded May 1, 2018
From: SILICON VALLEY BANK
To: EXTREME NETWORKS, INC.
Reel/Frame 046051/0775 →
BANKRUPTCY COURT ORDER RELEASING ALL LIENS INCLUDING THE SECURITY INTEREST RECORDED AT REEL/FRAME 029608/0256 Recorded Dec 15, 2017
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
To: AVAYA INC.
Reel/Frame 044891/0801 →
BANKRUPTCY COURT ORDER RELEASING ALL LIENS INCLUDING THE SECURITY INTEREST RECORDED AT REEL/FRAME 030083/0639 Recorded Dec 15, 2017
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
To: AVAYA INC.
Reel/Frame 045012/0666 →
BANKRUPTCY COURT ORDER RELEASING ALL LIENS INCLUDING THE SECURITY INTEREST RECORDED AT REEL/FRAME 041576/0001 Recorded Dec 15, 2017
From: CITIBANK, N.A.
To: AVAYA INC.; AVAYA INTEGRATED CABINET SOLUTIONS INC.; OCTEL COMMUNICATIONS LLC (FORMERLY KNOWN AS OCTEL COMMUNICATIONS CORPORATION); VPNET TECHNOLOGIES, INC.
Reel/Frame 044893/0531 →
THIRD AMENDED AND RESTATED PATENT AND TRADEMARK SECURITY AGREEMENT Recorded Oct 31, 2017
From: EXTREME NETWORKS, INC.
To: SILICON VALLEY BANK
Reel/Frame 044639/0300 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 15, 2017
From: AVAYA INC.; AVAYA COMMUNICATION ISRAEL LTD; AVAYA HOLDINGS LIMITED
To: EXTREME NETWORKS, INC.
Reel/Frame 043569/0047 →
SECOND AMENDED AND RESTATED PATENT AND TRADEMARK SECURITY AGREEMENT Recorded Jul 14, 2017
From: EXTREME NETWORKS, INC.
To: SILICON VALLEY BANK
Reel/Frame 043200/0614 →
SECURITY INTEREST Recorded Jan 27, 2017
From: AVAYA INC.; AVAYA INTEGRATED CABINET SOLUTIONS INC.; OCTEL COMMUNICATIONS CORPORATION; VPNET TECHNOLOGIES, INC.
To: CITIBANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041576/0001 →
SECURITY AGREEMENT Recorded Mar 13, 2013
From: AVAYA, INC.
To: BANK OF NEW YORK MELLON TRUST COMPANY, N.A., THE
Reel/Frame 030083/0639 →
SECURITY AGREEMENT Recorded Jan 10, 2013
From: AVAYA, INC.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 029608/0256 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 5, 2012
From: ASSARPOUR, HAMID
To: AVAYA INC.
Reel/Frame 028899/0348 →
Continuity (1)
Related Publication 20140006757A1 · Jan 2, 2014