IP Library Granted Patent US 9,299,568
Granted Patent B2
US 9,299,568 · App. 13/539,461 · Granted Mar 29, 2016

SONOS ONO stack scaling

Inventors: Fredrick Jenne (Sunnyvale, CA); Sagy Levy (Zichron-Yoakev, IL); Krishnaswamy Ramkumar (San Jose, CA)
Assignee: Cypress Semiconductor Corporation
H01L21/28282H01L21/3143H01L29/513H01L29/518H01L29/66833H01L29/792
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Quick Facts
Patent No.
US 9,299,568
App. No.
13/539,461
Granted
Mar 29, 2016
Kind
B2
Abstract

A method of scaling a nonvolatile trapped-charge memory device and the device made thereby is provided. In an embodiment, the method includes forming a channel region including polysilicon electrically connecting a source region and a drain region in a substrate. A tunneling layer is formed on the substrate over the channel region by oxidizing the substrate to form an oxide film and nitridizing the oxide film. A multi-layer charge trapping layer including an oxygen-rich first layer and an oxygen-lean second layer is formed on the tunneling layer, and a blocking layer deposited on the multi-layer charge trapping layer. In one embodiment, the method further includes a dilute wet oxidation to densify a deposited blocking oxide and to oxidize a portion of the oxygen-lean second layer.

Claims (22)

1. A method of fabricating a nonvolatile trapped-charge memory device, comprising:

forming a channel region in a substrate, the channel region electrically connecting a source region and a drain region in the substrate, wherein the channel region comprises polysilicon;

forming a tunneling layer on the substrate over the channel region, wherein forming the tunneling layer comprises oxidizing the substrate to form an oxide film and nitridizing the oxide film;

forming a multi-layer charge trapping layer comprising an oxygen-rich first layer on the tunneling layer and an oxygen-lean second layer over the first layer; and

forming a blocking layer on the multi-layer charge trapping layer,

wherein forming the multi-layer charge trapping layer further comprises forming an anti-tunneling layer comprising an oxide separating the first layer from the second layer.

2. The method of claim 1 , wherein forming the channel region comprises recrystallizing the polysilicon.

3. The method of claim 1 , further comprising densifying the blocking layer with an oxidizing anneal, wherein the oxidizing anneal oxidizes a portion of the oxygen-lean second layer of the multi-layer charge trapping layer proximate to the blocking layer.

4. The method of claim 1 , wherein forming the tunneling layer further comprises reoxidizing the nitridized oxide film by exposing the substrate to O 2 .

5. The method of claim 4 , wherein forming the tunneling layer further comprises renitridizing the reoxidized nitridized oxide film by exposing the substrate to NO.

6. The method of claim 1 , wherein at least one of the first layer and second layer of the multi-layer charge trapping layer comprise oxynitride.

7. A method of fabricating a nonvolatile trapped-charge memory device, comprising:

forming a channel region in a substrate;

forming a tunneling layer over the channel region, wherein forming the tunneling layer comprises oxidizing a surface of the substrate to form an oxide film and nitridizing the oxide film; and

forming a multi-layer charge trapping layer on the tunneling layer, the multi-layer charge trapping layer comprising an oxygen-rich first layer, an oxygen-lean second layer, and an anti-tunneling layer comprising an oxide separating the first layer from the second layer.

8. The method of claim 7 , further comprising forming a blocking layer on the multi-layer charge trapping layer.

9. The method of claim 8 , further comprising densifying the blocking layer with an oxidizing anneal, wherein the oxidizing anneal oxidizes at least a portion of the oxygen-lean second layer of the multi-layer charge trapping layer proximate to the blocking layer.

10. The method of claim 7 , wherein the channel region comprises polysilicon.

11. The method of claim 10 , wherein forming the channel region comprises recrystallizing the polysilicon.

12. The method of claim 7 , wherein forming the tunneling layer further comprises reoxidizing the nitridized oxide film by exposing the substrate to O 2 .

13. The method of claim 12 , wherein forming the tunneling layer further comprises renitridizing the reoxidized nitridized oxide film by exposing the substrate to NO.

14. The method of claim 7 , wherein at least one of the first layer and second layer of the multi-layer charge trapping layer comprise oxynitride.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
RELEASE OF SECURITY INTEREST Recorded May 7, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 049109/0573 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 4, 2019
From: CYPRESS SEMICONDUCTOR CORPORATION
To: LONGITUDE FLASH MEMORY SOLUTIONS LTD.
Reel/Frame 049086/0803 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 19, 2012
From: JENNE, FREDRICK B.; LEVY, SAGY; RAMKUMAR, KRISHNASWAMY
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 028620/0504 →
Continuity (3)
Continuation In Part 11904506 · Sep 26, 2007
Provisional Application 60940384 · May 25, 2007
Related Publication 20130307052A1 · Nov 21, 2013