Wideband CMOS RMS power detection system
View Patent ↗A system includes a first circuit and a second circuit. The first circuit includes a first MOS transistor having a gate and a drain. The first circuit is configured to receive a radio frequency (RF) signal at the gate of the first MOS transistor. The drain of the first MOS transistor is configured to output a first current that is proportional to the square of the input voltage of the RF signal while receiving the RF signal. The second circuit includes a second MOS transistor having a source configured to receive a first current from the first circuit. The second MOS transistor is biased in a triode region and has a channel resistance between the source and a drain. The second circuit is configured to output a voltage proportional to the value of the power of the RF signal received by the first circuit.
1. A system comprising:
a) a first circuit including a first MOS transistor having a gate for receiving a radio frequency (RF) signal and having a drain for outputting a first current that is proportional to a square of a voltage of the RF signal in response to receiving the RF signal,
b) a second circuit connected to the first circuit, the second circuit including a second MOS transistor biased in a triode region and having a source for receiving the first current from the first circuit,
c) wherein the second circuit outputs a voltage proportional to a value of the power of the RF signal received by the first circuit, the output voltage being a function of the first current and a channel resistance between a source and a drain of the second MOS transistor.
2. The system of claim 1 , further comprising: a correction loop connected to a gate of the second MOS transistor and to an output of the second circuit for maintaining the second MOS transistor biased in the triode region.
3. The system of claim 2 , wherein the correction loop varies the voltage applied to the gate of the second MOS transistor based in part on the output voltage of the second circuit.
4. The system of claim 2 , wherein the second circuit includes a low-pass filter connected to one of a drain or a source of the second MOS transistor, the low-pass filter removing a high-frequency component from the received RF signal.
5. The system of claim 1 , wherein the second MOS transistor is disposed within a feedback loop of an operation amplifier buffer having an input coupled to an output of the first circuit.
6. The system of claim 1 , wherein the first and second circuits have respective configurations such that the output voltage of the second circuit is proportional to the power of the RF signal received by the first circuit regardless of process variations within a range of process variations of a process that forms the first and second circuits.
7. The system of claim 1 , wherein the first circuit includes a first current mirror including the first MOS transistor.
8. The system of claim 7 , wherein the first circuit includes a second current mirror for generating a DC bias current to be subtracted from the first current.
9. The system of claim 1 , wherein the first circuit includes a pre-amplifier for increasing the voltage of the RF signal.
10. The system of claim 1 , wherein the first circuit includes an attenuator for attenuating the voltage of the RF signal.
11. The system of claim 1 , further comprising a calibration circuit connected to the first and second circuits for removing an error voltage from the output of the second circuit.
12. A method of detecting the power of an RF signal, comprising:
a) generating a first current proportional to a square of a voltage of the RF signal in response to receiving the RF signal at a gate of a MOS transistor of a first circuit;
b) generating a second current in a second circuit, the second current being proportional to the square of the voltage of the RF signal minus a DC offset of the RF signal;
c) receiving the second current at a source of a second MOS transistor that is biased in a triode region;
d) outputting a second voltage from the second circuit, the second voltage being proportional to the power of the RF signal received by the first circuit and being a function of the second current and a channel resistance between a source and a drain of the second MOS transistor.
13. The method of claim 12 , further comprising f) filtering the output voltage through a low-pass filter to remove a high-frequency component.
14. The method of claim 12 , wherein generating a second current includes: i) generating a DC bias current in the first circuit; and ii) subtracting the DC bias current from the first current at a first node.
15. The method of claim 12 , further comprising f) amplifying the received RF signal prior to receiving the RF signal at the gate of the first MOS transistor.
16. The method of claim 12 , further comprising f) attenuating the received RF signal prior to receiving the RF signal at the gate of the first MOS transistor.
17. The method of claim 12 , further comprising f) applying a bias voltage at a gate of the second MOS transistor to maintain the second MOS transistor in a triode region, wherein the bias voltage is based in part on a threshold voltage of the second transistor.
18. The method of claim 17 , wherein the bias voltage is based in part on a threshold voltage of the second MOS transistor.
19. The method of claim 12 , further comprising f) calibrating the output of the second circuit.
20. The method of claim 19 , wherein calibrating includes: i) storing the output voltage of the second circuit in a register when the first circuit is not receiving an RF signal; and ii) subtracting the stored output of the second circuit from an output voltage of the second circuit when the first circuit is receiving an RF signal.