METHOD AND APPARATUS FOR VIDEO CODING AND DECODING

1 . A method comprising:

receiving a first sequence of access units and a second sequence of access units;

decoding at least one access unit of the first sequence of access units;

decoding a first decodable access unit of the second sequence of access units;

determining whether a next decodable access unit in the second sequence of access units can be decoded before at least one of a decoding time of the next decodable access unit in the second sequence of access units and an output time of the next decodable access unit in the second sequence of access units; and

skipping decoding of the next decodable access unit based on determining that the next decodable access unit cannot be decoded before the at least one of the decoding time and the output time of the next decodable access unit.

2 . The method according to claim 1 , further comprising:

skipping decoding of any such access units in the second sequence of access units that depend on the next decodable access unit.

3 . The method according to claim 1 , further comprising:

decoding the next decodable access unit based on determining that the next decodable access unit can be decoded before the at least one of the decoding time and the output time of the next decodable access unit.

4 . The method according to claim 1 , further comprising:

receiving instructions of an alternative startup sequence for the second sequence of access units;

using the alternative startup sequence in said determining.

5 . The method according to claim 1 , wherein

the first sequence of access units is a subset of a first representation and the second sequence of access units is a subset of a second representation,

the first representation and the second representation originating from essentially the same media content, and

output times of the first sequence of access units having at least partly different range than output times of the second sequence of access units;

the method further comprising:

requesting transmission of the first sequence of access units prior to receiving the first sequence of access units,

determining to request transmission of the second sequence of access units rather than subsequent access units of the first representation, and

requesting transmission of the second sequence of access units prior to receiving the second sequence of access units.

6 . An apparatus comprising at least one processor and at least one memory including computer program code, the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus to:

decode at least one access unit of a first sequence of access units;

decode a first decodable access unit of a second sequence of access units;

determine whether a next decodable access unit in the second sequence of access units can be decoded before at least one of a decoding time of the next decodable access unit in the second sequence of access units and an output time of the next decodable access unit in the second sequence of access units; and

skip decoding of the next decodable access unit based on determining that the next decodable access unit cannot be decoded before the at least one of the decoding time and the output time of the next decodable access unit.

7 . The apparatus according to claim 6 , said at least one memory stored with code thereon, which when executed by said at least one processor, further causes the apparatus to:

skip decoding of any such access units in the second sequence of access units that depend on the next decodable access unit.

8 . The apparatus according to claim 6 , said at least one memory stored with code thereon, which when executed by said at least one processor, further causes the apparatus to:

decode the next decodable access unit based on determining that the next decodable access unit can be decoded before the at least one of the decoding time and the output time of the next decodable access unit.

9 . The apparatus according to claim 6 , said at least one memory stored with code thereon, which when executed by said at least one processor, further causes the apparatus to:

receive instructions of an alternative startup sequence for the second sequence of access units;

use the alternative startup sequence in said determining.

10 . An apparatus comprising at least one processor and at least one memory including computer program code, the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus to:

encapsulate at least one decodable access unit of a first sequence of access units for transmission;

encapsulate a first decodable access unit of a second sequence of access units for transmission;

determine whether a next decodable access unit in the second sequence of access units can be encapsulated before at least one of a decoding time of the next decodable access unit in the second sequence of access units and a transmission time of the next decodable access unit; and

skip encapsulation of the next decodable access unit based on determining that the next decodable access unit cannot be encapsulated before the at least one of the decoding time and the transmission time of the next decodable access unit.