Handling a failed processor of multiprocessor information handling system
View Patent ↗A method for handling a failed processor of a multiprocessor system, the multiprocessor system comprising at least two processors interconnected by processor interconnects for transactions between processors, the processors comprising a first processor and a second processor, the first processor being set as a default boot processor in response to a boot-up operation of the multiprocessor system. The method comprises: detecting and receiving, via a baseboard management module, health information of the at least two processors; providing a multiplexer operative to switch between the at least two processors, the multiplexer being coupled to the baseboard management module and respectively to the at least two processors; and, in response to the health information indicating the first processor has failed, setting, via a processor ID controller, the second processor as the default boot processor and enabling, via the baseboard management module, the multiplexer to switch to the second processor.
1. A method for handling a failed processor of a multiprocessor information handling system, the multiprocessor information handling system comprising at least two processors interconnected by processor interconnects for facilitating transactions of the processors, the at least two processors comprising a first processor and a second processor, the first processor being set as a default boot processor in response to a boot-up operation of the multiprocessor information handling system, and the system further comprising a first processor socket for accommodating the first processor and a second processor socket for accommodating the second processor, the method comprising:
detecting and receiving, via a baseboard management controller, health information of the at least two processors;
providing a multiplexer operative to switch between the at least two processors, the multiplexer being coupled to the baseboard management controller and respectively to the at least two processors; and
in response to the health information indicating the first processor has failed, setting, via a processor ID controller, the second processor as the default boot processor and enabling, via the baseboard management controller, the multiplexer to switch to the second processor, wherein the processor ID controller comprises a processor socket ID controller for setting either the first processor received in the first processor socket as the default boot processor or the second processor received in the second processor socket as the default boot processor.
2. The method of claim 1 , wherein the system further comprises:
an I/O device; and
an I/O unit coupled between the I/O device and the multiplexer for facilitating the transactions, wherein the I/O unit is coupled to the baseboard management controller and respectively to the at least two processors;
a RTMM module coupled to the baseboard management controller and respectively to the at least two processors, wherein the RTMM module enables the baseboard management controller to access the health information; and
a BIOS for booting the at least two processors.
3. The method of claim 2 , wherein the RTMM module is respectively coupled to the at least two processors via a digital interconnect selected from a PECI bus and an RAPL bus.
4. The method of claim 2 , further comprising:
the baseboard management controller receiving a POST complete command from the BIOS; and
the baseboard management controller accessing the health information via the digital interconnect to confirm the first processor has failed.
5. The method of claim 2 , further comprising:
in response to the second processor being set as the default boot processor, the baseboard management controller triggering a system reset to the I/O unit, and the I/O unit sending a CPU reset to the first processor.