Non-volatile memory device and method of manufacturing the same
A non-volatile memory device includes first and second vertical channel layers generally protruding upwardly from a semiconductor substrate substantially in parallel; a first gate group configured to include a plurality of memory cell gates which are stacked substantially along the first vertical channel layer and are isolated from each other with an interlayer insulating layer interposed substantially between the memory cell gates; a second gate group configured to include a plurality of memory cell gates which are stacked substantially along the second vertical channel layer and are isolated from each other with the interlayer insulating layer interposed substantially between the memory cell gates; a pipe channel layer configured to couple the first and the second vertical channel layers; and a channel layer extension part generally extended from the pipe channel layer to the semiconductor substrate and configured to couple the pipe channel layer and the semiconductor substrate.
1. A non-volatile memory device, comprising:
a first vertical channel layer and a second vertical channel layer, both of which, generally protrude upwardly from a semiconductor substrate substantially in parallel;
a first gate group configured to include a plurality of memory cell gates which are stacked substantially along the first vertical channel layer and are isolated from each other with an interlayer insulating layer interposed substantially between the memory cell gates;
a second gate group configured to include a plurality of memory cell gates which are stacked substantially along the second vertical channel layer and are isolated from each other with the interlayer insulating layer interposed substantially between the memory cell gates;
a pipe channel layer above the semiconductor substrate and configured to couple the first vertical channel layer and the second vertical channel layer; and
stack layers formed along outer walls of the first vertical channel layer, the second vertical channel layer and the pipe channel layer,
wherein the pipe channel layer includes an extension part passing through the stack layers and coupled to the semiconductor substrate.
2. The non-volatile memory device of claim 1 , further comprising:
a first pipe gate formed on the pipe channel layer to substantially surround the first vertical channel layer; and
a second pipe gate formed on the pipe channel layer to substantially surround the second vertical channel layer.
3. The non-volatile memory device of claim 1 , further comprising:
a first pipe gate formed to substantially surround the pipe channel layer; and
a second pipe gate over the pipe channel layer to substantially surround the first vertical channel layer and the second vertical channel layer.
4. The non-volatile memory device of claim 3 , wherein the first pipe gate is formed substantially within the semiconductor substrate or generally over the semiconductor substrate.
5. The non-volatile memory device of claim 1 , further comprising a P-type impurity region formed within the extension part of the pipe channel layer and a surface of the semiconductor substrate.
6. The non-volatile memory device of claim 1 , further comprising a first impurity region formed within the extension part of the pipe channel layer.
7. The non-volatile memory device of claim 6 , wherein the first impurity region is a P-type impurity region.
8. The non-volatile memory device of claim 1 , further comprising a second impurity region formed within a surface of the pipe channel layer substantially between the first and the second gate groups.
9. The non-volatile memory device of claim 8 , wherein the second impurity region is an N-type impurity region.
10. The non-volatile memory device of claim 1 , further comprising a metal silicide layer formed substantially in a surface of the pipe channel layer substantially between the first and the second gate groups.
11. The non-volatile memory device of claim 1 , further comprising a metal silicide layer formed generally on sidewalls of the memory cell gates.