Method and structure of wafer level encapsulation of integrated circuits with cavity
The present invention is related shielding integrated devices using CMOS fabrication techniques to form an encapsulation with cavity. The integrated circuits are completed first using standard IC processes. A wafer-level hermetic encapsulation is applied to form a cavity above the sensitive portion of the circuits using IC-foundry compatible processes. The encapsulation and cavity provide a hermetic inert environment that shields the sensitive circuits from EM interference, noise, moisture, gas, and corrosion from the outside environment.
1. A method for fabricating an integrated circuit, the method comprising:
providing a first semiconductor substrate having a first surface region;
forming one or more CMOS integrated circuit (IC) devices provided on a CMOS IC device region overlying the first surface region, the CMOS IC device region having a CMOS surface region;
forming a dielectric layer overlying the CMOS surface region;
forming a sacrificial layer overlying a portion of the dielectric layer;
forming an enclosure layer overlying the sacrificial layer;
removing the sacrificial layer via an ashing process to form a void region between the portion of the dielectric layer and the enclosure layer;
sealing the void region in a predetermined environment, wherein sealing the void region comprises forming a barrier material overlying at least the void region to hermetically seal the one or more CMOS IC devices;
forming a seal ring encircling the CMOS IC devices, the seal ring being electrically coupled with the barrier material to shield the one or more CMOS IC devices.
2. The method of claim 1 wherein the one or more CMOS IC devices are formed using a standard CMOS process from a semiconductor foundry.
3. The method of claim 1 wherein the enclosure layer comprises titanium material, the titanium material being activated as a getter layer.
4. The method of claim 1 wherein the enclosure layer is selected from a metal, a semiconductor material, an amorphous silicon material, a dielectric layer, or a combination of these layers.
5. The method of claim 1 wherein forming the void region comprises a forming a void volume comprising vacuum, air, an inert material, or an inert gas.
6. The method of claim 1 wherein forming the void region comprises a forming a void volume that is characterized by a dielectric constant of 1.2 and less.
7. The method of claim 1 wherein forming the one or more CMOS IC devices comprises forming at least one of an RC timing circuit, LC timing circuit, RF circuit, or analog circuit.
8. A method for forming high quality silicon material for photovoltaic devices, the method comprising:
providing a semiconductor substrate having a surface region, a first portion and a second portion;
forming one or more CMOS integrated circuit (IC) on the first portion of the semiconductor substrate;
forming one or more sensitive integrated circuit (IC) modules provided on a second portion of the semiconductor substrate, wherein the one or more sensitive integrated circuit (IC) modules are sensitive to ambient interference and changes;
forming a seal ring encircling the one or more sensitive integrated circuit modules;
forming one or more dielectric layers overlying the one or more CMOS IC devices and the one or more sensitive IC modules to form a passivation structure overlying the one or more CMOS IC devices and the one or more sensitive IC modules;
forming a sacrificial layer overlying a portion of the one or more dielectric layers;
forming an enclosure layer overlying the sacrificial layer;
removing the sacrificial layer via an ashing process to form a void region between the portion of the dielectric layer and the enclosure layer; and
sealing the void region in a predetermined environment.
9. The method of claim 8 wherein sealing the void region comprises forming a barrier material overlying at least the void region to hermetically seal the one or more sensitive IC modules while maintaining the void region overlying the one or more dielectric layers.
10. The method of claim 9 wherein the barrier material is electrically coupled with the seal ring to shield the one or more sensitive IC modules.
11. The method of claim 9 further comprising one or more dielectric layers overlying the barrier material.
12. The method of claim 9 wherein the barrier material is selected from a group consisting of: amorphous silicon, polysilicon, silicon germanium, and germanium.
13. The method of claim 9 wherein the barrier material is selected from a group consisting of: tungsten, platinum, titanium, titanium nitride, titanium tungsten, copper, tantalum, aluminum, or aluminum titanium alloy.
14. The method of claim 9 wherein the barrier material is selected from a group consisting of: an oxide, a nitride, an oxynitride, a spin-on-glass, and a spray-on glass.
15. The method of claim 9 wherein the barrier material comprises a semiconductor, a metal, or a dielectric.
16. The method of claim 8 wherein the void region comprises a void volume selected from a group consisting of: air, an inert material, an inert gas, a vacuum.
17. The method of claim 16 wherein the void volume is characterized by a dielectric constant of 1.2 and less.
18. The method of claim 16 wherein the one or more sensitive IC modules comprises one or more of an RC timing circuit, LC timing circuit, RF circuit, or analog circuit.