System for display images and fabrication method thereof
View Patent ↗A system for displaying images including a display panel and a fabrication method thereof are provided. The method includes forming a first gate line and a second gate line at each row of pixels of the display panel, wherein the first gate lines and the second gate lines are separated and electrically isolated from each other. A first insulating layer is formed to cover the first gate lines and the second gate lines, and a plurality of via holes are formed in the first insulating layer to expose the first gate lines and the second gate lines. Then, a first conductive pattern is formed on the first insulating layer, such that the first gate line at each row of the pixels is electrically connected to the second gate line at an adjacent row of the pixels, by the first conductive pattern, through the via holes.
1. A method of fabricating a system for displaying images, including forming a display panel, having a plurality of pixels, the method comprising:
forming a first gate line and a second gate line at each row of the pixels, wherein each of the first gate lines and each of the second gate lines are separated and electrically isolated from each other, and the first gate line and the second gate line at each row of the pixels are two parallel gate lines;
forming a first insulating layer, covering the first gate lines and the second gate lines;
forming a plurality of via holes in the first insulating layer to expose the first gate lines and the second gate lines; and
forming a first conductive pattern on the first insulating layer, wherein the first gate line at each row of the pixels is electrically connected to the second gate line at an adjacent row of the pixels, by the first conductive pattern, through the via holes.
2. The method as claimed in claim 1 , further comprising:
forming a second conductive pattern between the first insulating layer and the first conductive pattern, wherein the second conductive pattern is located between the first gate line and the second gate line;
forming a second insulating layer between the second conductive pattern and the first conductive pattern; and
forming a plurality of via holes in the second insulating layer to expose the first gate lines, the second conductive pattern and the second gate lines separately,
wherein the first gate line at the each row of the pixels is electrically connected to the second gate line at the adjacent row of the pixels and the second conductive pattern by the first conductive pattern, through the via holes in the first insulating layer and the via holes in the second insulating layer.
3. The method as claimed in claim 2 , wherein the second conductive pattern is separated from the first gate line and the second gate line with a gap or partially overlaps the first gate line and the second gate line.
4. The method as claimed in claim 3 , wherein the second conductive pattern partially overlaps the first gate line and the second gate line, and a laser beam is used to irradiate the overlapped portions between the second conductive pattern and the first gate line and the second gate line, wherein due to the laser beam, the second conductive pattern is electrically connected with the first gate line and the second gate line.
5. The method as claimed in claim 2 , wherein the second insulating layer comprises one or more than one via hole formed therein to expose the second conductive pattern.
6. The method as claimed in claim 5 , wherein the second insulating layer only has one via hole to expose the second conductive pattern, and the one via hole has a length which is longer than 50% of the length of the second conductive pattern.
7. The method as claimed in claim 2 , wherein the materials of the first and the second conductive patterns comprise a transparent conductive material or a metal material.
8. The method as claimed in claim 1 , wherein the first gate line and the second gate line separately have an extended portion between the first gate line and the second gate line, and the via holes in the first insulating layer are formed on the extended portions of the first gate line and the second gate line.
9. The method as claimed in claim 8 , wherein the extended portion of the first gate line is aligned with or parallel to the extended portion of the second gate line.
10. The method as claimed in claim 1 , wherein the via holes in the first insulating layer are directly formed on the first gate line and the second gate line.
11. A system for displaying images, comprising;
a display panel, having a plurality of pixels, the display panel comprising:
a first gate line and a second gate line disposed at each row of the pixels, wherein each of the first gate lines and each of the second gate lines are separated from each other, and the first gate line and the second gate line at each row of the pixels are two parallel gate lines;
a first insulating layer disposed over the first gate lines and the second gate lines;
a plurality of via holes disposed in the first insulating layer to expose the first gate lines and the second gate lines separately; and
a first conductive pattern disposed on the first insulating layer, wherein the first gate line at each row of the pixels is electrically connected to the second gate line at an adjacent row of the pixels, by the first conductive pattern, through the via holes.
12. The system as claimed in claim 11 , further comprising:
a second conductive pattern disposed between the first insulating layer and the first conductive pattern, wherein the second conductive pattern is located between the first gate line and the second gate line;
a second insulating layer disposed between the second conductive pattern and the first conductive pattern; and
a plurality of via holes disposed in the second insulating layer to expose the first gate lines, the second conductive pattern and the second gate lines separately,
wherein the first gate line at the each row of the pixels is electrically connected to the second gate line at the adjacent row of the pixels and the second conductive pattern by the first conductive pattern, through the via holes in the first insulating layer and the via holes in the second insulating layer.
13. The system as claimed in claim 12 , wherein the second conductive pattern is separated from the first gate line and the second gate line with a gap or partially overlaps the first gate line and the second gate line.
14. The system as claimed in claim 12 , wherein the second insulating layer comprises one or more than one via hole formed therein to expose the second conductive pattern.
15. The system as claimed in claim 14 , wherein the second insulating layer only has one via hole to expose the second conductive pattern, and the one via hole has a length which is longer than 50% of the length of the second conductive pattern.
16. The system as claimed in claim 11 , wherein the materials of the first and the second gate lines comprise a metal material.
17. The system as claimed in claim 12 , wherein the materials of the first and the second conductive patterns comprise a transparent conductive material or a metal material.
18. The system as claimed in claim 11 , wherein the first gate line and the second gate line separately have an extended portion between the first gate line and the second gate line, and the via holes in the first insulating layer are disposed on the extended portion of the first gate line and the extended portion of the second gate line, wherein the extended portion of the first gate line is aligned with or parallel to the extended portion of the second gate line.
19. The system as claimed in claim 11 , wherein the via holes in the first insulating layer are directly disposed on the first gate line and the second gate line.
20. The system as claimed in claim 11 , further comprising an electronic device, wherein the electronic device comprises:
a display, including the display panel; and
a control unit coupled to the display to provide input to the display such that the display displays images.