Solid state storage element and method
View Patent ↗A method and system for storing and retrieving data using flash memory devices. One example system includes an apparatus within a flash memory configuration. The flash memory configuration includes a plurality of memory cells, where each memory cell has a charge storage capacity for use in implementing digital storage. The apparatus includes a processing arrangement configured to access each of the memory cells in a write operation and a read operation. The apparatus also includes an instruction set for instructing the processor to impose target charge levels for defining a plurality of data values for each of the memory cells. The target charge levels are programmably movable with respect to the charge storage capacity.
1. In a memory configuration, a calibration method comprising:
for each memory symbol in a set of memory symbols, where each memory symbol in the set of memory symbols identifies a target charge level from a plurality of target charge levels associated with a memory cell:
writing the memory symbol to a known location within the memory cell by applying to the memory cell the target charge level identified for the memory symbol;
sensing a charge level stored within the memory cell at the known location;
comparing the sensed charge level to the applied target charge level to determine a difference value;
calculating a performance characteristic for the memory symbol using the difference value; and
storing the performance characteristic for the memory symbol into a data structure.
2. The calibration method of claim 1 , further comprising:
reading an uncorrected memory symbol from the memory cell, the uncorrected memory symbol identifying a charge level within the memory cell;
converting the uncorrected memory symbol to uncorrected code data; and
applying the performance characteristic to the uncorrected code data to generate corrected code data.
3. The calibration method of claim 1 , wherein the memory configuration is operable to store data in analog form.
4. The calibration method of claim 1 , wherein the memory configuration comprises flash memory.
5. The calibration method of claim 1 , wherein the values of the performance characteristics are used for more than one memory cell of the cell array device.
6. The calibration method of claim 1 , wherein one of the target charge levels is associated with an adjustable discrimination level.
7. The calibration method of claim 1 wherein the number of memory symbols in the set of memory symbols is equal to the number of target charge levels associated with the memory cell.
8. The calibration method of claim 1 , wherein the number of target charge levels associated with the memory cell is a non-integer power of two.
9. The calibration method of claim 1 , wherein at least one calculated performance characteristic is generalized for at least one other memory symbol in the set of memory symbols.
10. A method for writing data, comprising:
reading user data symbols from a buffer;
processing and appending the user data symbols with a set of additional data symbols for parity so as to generate a block of user data symbols plus a set of parity symbols;
encoding the user data symbols and parity symbols using an encoding process;
encoding a stream of symbols output by the encoding process to produce a stream of code symbols;
encoding one or more memory symbols generated based on the stream of code symbols; and
transferring one or more memory symbols to a memory configuration.
11. The method of claim 10 , further comprising, prior to encoding one or more memory symbols based on the stream of code symbols, precompensating one or more code symbols in the stream of code symbols to produce one or more memory symbols.
12. The method of claim 11 , wherein precompensating one or more code symbols is performed using data produced by a calibration process.
13. The method of claim 10 , wherein the memory configuration is operable to store data in analog form.
14. The method of claim 13 , wherein the memory configuration comprises flash memory.
15. A method for reading data, comprising:
reading one or more memory symbols from a memory cell of a memory configuration;
converting the memory symbols to a stream of code symbols;
sequence decoding the stream of code symbols to produce a stream of data symbols;
applying a decoding process to the stream of data symbols;
performing one of the following depending upon the outcome of the decoding process:
detect and correct any correctable errors in the stream of data symbols, and then transfer the data symbols to a buffer;
detect no errors in the stream of data symbols, and then transfer the data symbols to the buffer; or
detect more errors in the stream of data symbols than can be corrected by the decoding process, and then abort.
16. The method of claim 15 , further comprising, prior to sequence decoding the stream of code symbols to produce a stream of data symbols, post-compensating one or more code symbols of the stream of code symbols to produce a stream of post-compensated code symbols that are subsequently decoded.
17. The method of claim 16 , wherein post-compensating one or more code symbols is performed using data produced by a calibration process.
18. The method of claim 15 , wherein the memory cell is operable to store data in analog form.
19. The method of claim 18 , wherein the memory configuration comprises flash memory.
20. The method of claim 15 , wherein converting the memory symbols to a stream of code symbols includes identifying a number of target charge levels associated with the memory cell.
21. A computer memory storing instructions configured to cause a computing device to perform a calibration method in a memory configuration, the method comprising:
for each memory symbol in a set of memory symbols, where each memory symbol in the set of memory symbols identifies a target charge level from a plurality of target charge levels associated with a memory cell:
writing the memory symbol to a known location within the memory cell by applying to the memory cell the target charge level identified for the memory symbol;
sensing a charge level stored within the memory cell at the known location;
comparing the sensed charge level to the applied target charge level to determine a difference value;
calculating a performance characteristic for the memory symbol using the difference value; and
storing the performance characteristic for the memory symbol into a data structure.
22. A computer memory storing instructions configured to cause a computing device to perform a method for writing data, the method comprising:
reading user data symbols from a buffer;
processing and appending the user data symbols with a set of additional data symbols for parity so as to generate a block of user data symbols plus a set of parity symbols;
encoding the user data symbols and parity symbols using an encoding process;
encoding a stream of symbols output by the encoding process to produce a stream of code symbols;
encoding one or more memory symbols generated based on the stream of code symbols; and
transferring one or more memory symbols to a memory configuration.
23. A computer memory storing instructions configured to cause a computing device to perform a method for reading data, the method comprising:
reading one or more memory symbols from a memory cell of a memory configuration;
converting the memory symbols to a stream of code symbols;
sequence decoding the stream of code symbols to produce a stream of data symbols;
applying a decoding process to the stream of data symbols;
performing one of the following depending upon the outcome of the decoding process:
detect and correct any correctable errors in the stream of data symbols, and then transfer the data symbols to a buffer;
detect no errors in the stream of data symbols, and then transfer the data symbols to the buffer; or
detect more errors in the stream of data symbols than can be corrected by the decoding process, and then abort.