Drain extended MOS transistor and method for fabricating the same
View Patent ↗A drain extended MOS (DEMOS) transistor including at least one of: (1) A p-type epitaxial layer grown over an n-type semiconductor substrate. (2) An n-type well formed in a portion of the epitaxial layer. (3) A p-type drift region formed in another portion of the epitaxial layer. (4) A p-type source region formed in the well. (5) A p-type drain region formed in the drift region and spaced apart from the source region inside the epitaxial layer. (6) An n-type channel region extending between the drift region and the source region. (7) A gate structure formed over the channel region. (8) An n-type buried layer having a contact surface with the well and the drift region and formed in the epitaxial layer. A region of the buried layer has surface contact with the drift region and has a relatively low dopant concentration compared to other regions.
1. A method of fabricating a DEMOS transistor, comprising:
providing a first conductive type silicon substrate;
forming a second conductive type buried layer having a different concentration distributions in portion of the silicon substrate;
forming an epitaxial silicon layer over the silicon substrate;
defining a second conductive type well and a first conductive type drift region in the epitaxial silicon layer;
forming a first conductive type source region and a second conductive type back gate in the second conductive type well;
forming a first conductive type expanded drain in the drift region,
wherein, in the forming of the second conductive type buried layer, the buried layer is formed such that a first region adjacent to the drift region has a lower dopant concentration than a second region, wherein the second region is outside of the first region.
2. The method of claim 1 , wherein the forming of the second conductive type buried layer comprises:
forming a pattern which opens the portion of the silicon substrate corresponding to the first region and the top of the silicon substrate corresponding to the second region;
forming a guard ring in the first region and forming a dopant region in the second region by performing a second conductive type dopant ion implantation process using a pattern;
removing the pattern; and
performing a thermal diffusion process to form the buried layer, wherein the first region has a relatively low dopant concentration compared to the second region.
3. The method of claim 1 , wherein said forming the second conductive type buried layer comprises forming a first conductive type buried layer between the second conductive type well and the second region.
4. The method of claim 1 , wherein the first conductive type is p-type and the second conductive type is n-type.