Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
View Patent ↗Structures include a tunneling device disposed over first and second lattice-mismatched semiconductor materials. Process embodiments include forming tunneling devices over lattice-mismatched materials.
1. A method comprising:
forming a resonant tunneling diode (RTD)-based static random access memory (SRAM) circuit, the RTD-based SRAM circuit having a perimeter defining an RTD-based SRAM cell area, the forming the RTD-based SRAM circuit comprising:
forming a transistor having a gate length above a substrate, the substrate including a first crystalline material, and
forming a first RTD proximate an opening disposed above the substrate, the opening comprising a non-crystalline sidewall, the first RTD being coupled to a source or a drain of the transistor, the first RTD including a crystalline material lattice-mismatched to the first crystalline material.
2. The method of claim 1 , wherein the RTD-based SRAM cell area is at least 33% smaller than a surface area of an SRAM circuit constructed using six transistors having a same gate length as the transistor in the RTD-based SRAM cell area.
3. The method of claim 1 , wherein the opening has a width, and the crystalline material has an external planar surface that at least partially interfaces with the non-crystalline sidewall, the external surface having a height greater than half the width.
4. The method of claim 1 further comprising forming a second RTD, the first RTD and the second RTD being coupled together.
5. The method of claim 4 , wherein the first RTD and the second RTD are coupled together serially.
6. The method of claim 1 , wherein a majority of defects arising from the lattice-mismatch terminate at a vertical surface of the crystalline material.
7. The method of claim 1 , wherein the opening comprising the non-crystalline sidewall is formed in a dielectric material.
8. A method comprising:
forming a first transistor on a substrate, the substrate comprising a first crystalline material;
forming a dielectric layer over the substrate, the dielectric layer having a first opening to the first crystalline material of the substrate; and
forming a first tunneling diode, the tunneling diode comprising a second crystalline material in the first opening, the second crystalline material being lattice mismatched to the first crystalline material, the first tunneling diode being electrically coupled to the first transistor.
9. The method of claim 8 , wherein the tunneling diode is a resonant tunneling diode (RTD) or a resonant interband tunneling diode (RITD).
10. The method of claim 8 further comprising forming a second tunneling diode comprising the second crystalline material in a second opening, the second opening being in the dielectric layer, the second tunneling diode being electrically coupled to the first transistor.
11. The method of claim 10 , wherein each of the first tunneling diode, the second tunneling diode, and a source/drain region of the first transistor are connected to a same electrical node.
12. The method of claim 10 , wherein the first opening and the second opening are formed over a doped region in the first crystalline material of the substrate, the doped region being electrically isolated through the substrate to a well of the first transistor, the second crystalline material in the first opening and in the second opening adjoining the doped region.
13. The method of claim 10 , wherein the first opening and the second opening are formed over a source/drain region of the first transistor in the first crystalline material of the substrate, the second crystalline material in the first opening and in the second opening adjoining the source/drain region.
14. The method of claim 8 , wherein the first transistor and the first tunneling diode are components of a static random access memory (SRAM) cell.
15. The method of claim 8 , wherein a source/drain region of the transistor is electrically coupled to the first tunneling diode.
16. The method of claim 8 , wherein a source/drain region of the transistor is electrically coupled to the first tunneling diode and to a resistor.
17. The method of claim 8 , wherein a source/drain region of the transistor is electrically coupled to the first tunneling diode and to a source/drain region of second transistor.
18. The method of claim 8 , wherein a source/drain region of the transistor is electrically coupled to the first tunneling diode and to a second tunneling diode.
19. The method of claim 8 , wherein the opening has a width, and the dielectric layer has a height, the height being equal to or greater half of the width.
20. A method comprising:
forming a tunneling diode structure in an opening of a dielectric layer over a substrate, the substrate comprising a first crystalline material, the tunneling diode structure comprising a second crystalline material lattice mismatched to the first crystalline material, the second crystalline material comprising defects arising from the lattice mismatch, a majority of the defects terminating at a sidewall of the second crystalline material; and
forming a magnetic tunnel junction structure over the tunneling diode, the magnetic tunnel junction structure comprising a magnetic pinned layer over the tunneling diode, a tunnel barrier layer over the magnetic pinned layer, and a magnetic free layer over the barrier layer.