Nonvolatile semiconductor memory device

1. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate;

first to third fin type stacked layer structures which each have first and second memory cells stacked in a first direction perpendicular to the surface of the semiconductor substrate and which each extend in a second direction parallel to the surface of the semiconductor substrate and which are arranged in a third direction perpendicular to the first and second directions, the third fin type stacked layer structure provided between the first and second fin type stacked layer structure;

a first assist gate transistor which comprises a first assist gate electrode covering first and second surfaces of the first fin type stacked layer structure facing each other in the third direction and a first surface of the third fin type stacked layer structure facing the first and second surfaces of the first fin type stacked layer structure in the third direction;

a second assist gate transistor which comprises a second assist gate electrode covering first and second surfaces of the second fin type stacked layer structure facing each other in the third direction and a second surface of the third fin type stacked layer structure facing the first and second surfaces of the second fin type stacked layer structure in the third direction; and

a third assist gate transistor which comprises a third assist gate electrode covering the first and second surfaces of the third fin type stacked layer structure facing each other in the third direction, the second surface of the first fin type stacked layer structure, and the first surface of the second fin type stacked layer structure,

wherein an on/off state of each of the first assist gate transistor, the second gate transistor, and the third assist gate transistor is controlled independently of each other,

each of first to third fin type stacked layer structures comprises first and second semiconductor layers stacked in the first direction,

the first and second memory cells are provided in corresponding to the first and second semiconductor layers,

the first and second assist gate electrodes are arranged side by side in the third direction, and are divided from each other on the surface of the third fin type stacked layer structure facing the surface of the semiconductor substrate in the first direction,

the first assist gate transistor has a double gate structure in the first fin type stacked layer structure, and has a single gate structure in the third fin type stacked layer structure,

the second assist gate transistor has the double gate structure in the second fin type stacked layer structure, and has the single gate structure in the third fin type stacked layer structure, and

the third assist gate transistor has the double gate structure in the third fin type stacked layer structure, and has the single gate structure in the first and second fin type stacked layer structures.

2. The device of claim 1 ,

wherein the first and second semiconductor layers in the third fin type stacked layer structure between the first and second assist gate electrodes comprise normally-on channels which are not dependent on the potentials of the first and second assist gate electrodes, respectively, and

the first and second semiconductor layers in the first and second fin type stacked layer structures adjacent to the third assist gate electrode in the third direction comprise the normally-on channels which are not dependent on the potential of the third assist gate electrode, respectively.

3. The device of claim 2 ,

wherein the normally-on channels comprise impurity regions in the first and second semiconductor layers, respectively.

4. The device of claim 1 ,

wherein the first and second semiconductor layers in the first fin type stacked layer structure adjacent to the first assist gate electrode comprise on/off channels which are dependent on the potential of the first assist gate electrode, respectively,

the first and second semiconductor layers in the second fin type stacked layer structure adjacent to the second assist gate electrode comprise on/off channels which are dependent on the potential of the second assist gate electrode, respectively, and

the first and second semiconductor layers in the third fin type stacked layer structure adjacent to the third assist gate electrode comprise on/off channels which are dependent on the potential of the third assist gate electrode, respectively.

5. The device of claim 1 , further comprising

a first beam which is connected to one end of each of the first to third fin type stacked layer structures in the second direction and which extends in the third direction and which comprises third and fourth semiconductor layers connected to the first and second semiconductor layers respectively.

6. The device of claim 5 ,

wherein the first to third assist gate transistors are disposed between the first beam and the first and second memory cells in the first to third fin type stacked layer structures.

7. The device of claim 5 ,

wherein the first to third assist gate transistors are disposed on the side of the first and second memory cells in the first to third fin type stacked layer structures opposite to the first beam.

8. The device of claim 6 , further comprising

a stack structure row which comprises the first to third fin type stacked layer structures; and

an electrode array which comprises the first to third assist gate electrodes,

wherein the electrode array has two or more rows on the stack structure row in the second direction, and

each row of the electrode array has a layout in which each electrode skips over one or more of the stack structure rows to extend in the third direction.

9. The device of claim 7 , further comprising

a stack structure row which comprises the first to third fin type stacked layer structures; and

an electrode array which comprises the first to third assist gate electrodes,

wherein the electrode array has two or more rows on the stack structure row in the second direction, and

each row of the electrode array has a layout in which each electrode skips over one or more of the stack structure rows to extend in the third direction.

10. The device of claim 5 , further comprising

a second beam which is connected to the other end of each of the first to third fin type stacked layer structures in the second direction and which extends in the third direction and which comprises third and fourth semiconductor layers connected to the first and second semiconductor layers, respectively.

11. The device of claim 5 , further comprising

first to third electrodes each connected to the other end of each of the first to third fin type stacked layer structures in the second direction.

12. The device of claim 1 ,

wherein the first and second assist gate transistors are disposed at a first end of each of the first and second memory cells in the first to third fin type stacked layer structures in the second direction,

the third assist gate transistor is disposed at a second end of each of the first and second memory cells in the first to third fin type stacked layer structures in the second direction.

13. The device of claim 1 , further comprising

a common electrode which passes through the first to third fin type stacked layer structures and which is connected to the first and second semiconductor layers.

14. The device of claim 1 ,

wherein each of the first to third assist gate transistors is an FET using the first and second semiconductor layers as channels.

15. The device of claim 1 ,

wherein each of the first and second memory cells is an FET which comprises a recording layer and a gate electrode and which uses the first and second semiconductor layers as channels and which changes in threshold in accordance with the state of the recording layer.

16. The device of claim 1 , further comprising

a third semiconductor layer which is disposed between the first and second semiconductor layers and which extends in the third direction,

wherein the first memory cell is a resistance change element disposed between the first and third semiconductor layers, and the second memory cell is a resistance change element disposed between the second and third semiconductor layers.

17. The device of claim 1 , further comprising

a fourth assist gate transistor which comprises a fourth assist gate electrode covering the first and second surfaces of the first fin type stacked layer structure facing each other in the third direction and the first surface of the third fin type stacked layer structure facing the first and second surfaces of the first fin type stacked layer structure in the third direction;

a fifth assist gate transistor which comprises a fifth assist gate electrode covering the first and second surfaces of the second fin type stacked layer structure facing each other in the third direction and the second surface of the third fin type stacked layer structure facing the first and second surfaces of the second fin type stacked layer structure in the third direction; and

a sixth assist gate transistor which comprises a sixth assist gate electrode covering the first and second surfaces of the third fin type stacked layer structure facing each other in the third direction, the second surface of the first fin type stacked layer structure, and the first surface of the second fin type stacked layer structure,

wherein the fourth and fifth assist gate electrodes are arranged side by side in the third direction, and are divided from each other on the surface of the third fin type stacked layer structure facing the surface of the semiconductor substrate in the first direction,

the fourth assist gate transistor has a double gate structure in the first fin type stacked layer structure, and has a single gate structure in the third fin type stacked layer structure,

the fifth assist gate transistor has the double gate structure in the second fin type stacked layer structure, and has the single gate structure in the third fin type stacked layer structure, and

the sixth assist gate transistor has the double gate structure in the third fin type stacked layer structure, and has the single gate structure in the first and second fin type stacked layer structures.

18. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate;

first to third fin type stacked layer structures which each have first and second memory cells stacked in a first direction perpendicular to the surface of the semiconductor substrate and which each extend in a second direction parallel to the surface of the semiconductor substrate and which are arranged in a third direction perpendicular to the first and second directions, the third fin type stacked layer structure provided between the first and second fin type stacked layer structure;

a first assist gate transistor which comprises a first assist gate electrode covering first and second surfaces of the first fin type stacked layer structure facing each other in the third direction and a first surface of the third fin type stacked layer structure facing the first and second surfaces of the first fin type stacked layer structure in the third direction;

a second assist gate transistor which comprises a second assist gate electrode covering first and second surfaces of the second fin type stacked layer structure facing each other in the third direction and a second surface of the third fin type stacked layer structure facing the first and second surfaces of the second fin type stacked layer structure in the third direction; and

a third assist gate transistor which comprises a third assist gate electrode covering the first and second surfaces of the third fin type stacked layer structure facing each other in the third direction, the second surface of the first fin type stacked layer structure, and the first surface of the second fin type stacked layer structure,

wherein each of first to third fin type stacked layer structures comprises first and second semiconductor layers stacked in the first direction,

the first and second memory cells are provided in corresponding to the first and second semiconductor layers,

the first and second assist gate electrodes are arranged side by side in the third direction, and are divided from each other on the surface of the third fin type stacked layer structure facing the surface of the semiconductor substrate in the first direction,

the first assist gate transistor has a double gate structure in the first fin type stacked layer structure, and has a single gate structure in the third fin type stacked layer structure,

the second assist gate transistor has the double gate structure in the second fin type stacked layer structure, and has the single gate structure in the third fin type stacked layer structure, and

the third assist gate transistor has the double gate structure in the third fin type stacked layer structure, and has the single gate structure in the first and second fin type stacked layer structures,

and further comprising:

a first beam which is connected to one end of each of the first to third fin type stacked layer structures in the second direction and which extends in the third direction and which comprises third and fourth semiconductor layers connected to the first and second semiconductor layers respectively, and

wherein the first to third assist gate transistors are disposed between the first beam and the first and second memory cells in the first to third fin type stacked layer structures.

19. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate;

first to third fin type stacked layer structures which each have first and second memory cells stacked in a first direction perpendicular to the surface of the semiconductor substrate and which each extend in a second direction parallel to the surface of the semiconductor substrate and which are arranged in a third direction perpendicular to the first and second directions, the third fin type stacked layer structure provided between the first and second fin type stacked layer structure;

a first assist gate transistor which comprises a first assist gate electrode covering first and second surfaces of the first fin type stacked layer structure facing each other in the third direction and a first surface of the third fin type stacked layer structure facing the first and second surfaces of the first fin type stacked layer structure in the third direction;

a second assist gate transistor which comprises a second assist gate electrode covering first and second surfaces of the second fin type stacked layer structure facing each other in the third direction and a second surface of the third fin type stacked layer structure facing the first and second surfaces of the second fin type stacked layer structure in the third direction; and

a third assist gate transistor which comprises a third assist gate electrode covering the first and second surfaces of the third fin type stacked layer structure facing each other in the third direction, the second surface of the first fin type stacked layer structure, and the first surface of the second fin type stacked layer structure,

wherein each of first to third fin type stacked layer structures comprises first and second semiconductor layers stacked in the first direction,

the first and second memory cells are provided in corresponding to the first and second semiconductor layers,

the first and second assist gate electrodes are arranged side by side in the third direction, and are divided from each other on the surface of the third fin type stacked layer structure facing the surface of the semiconductor substrate in the first direction,

the first assist gate transistor has a double gate structure in the first fin type stacked layer structure, and has a single gate structure in the third fin type stacked layer structure,

the second assist gate transistor has the double gate structure in the second fin type stacked layer structure, and has the single gate structure in the third fin type stacked layer structure, and

the third assist gate transistor has the double gate structure in the third fin type stacked layer structure, and has the single gate structure in the first and second fin type stacked layer structures,

and further comprising:

a first beam which is connected to one end of each of the first to third fin type stacked layer structures in the second direction and which extends in the third direction and which comprises third and fourth semiconductor layers connected to the first and second semiconductor layers respectively, and

wherein the first to third assist gate transistors are disposed between the first beam and the first and second memory cells in the first to third fin type stacked layer structures,

and further comprising:

a stack structure row which comprises the first to third fin type stacked layer structures; and

an electrode array which comprises the first to third assist gate electrodes,

wherein the electrode array has two or more rows on the stack structure row in the second direction, and

each row of the electrode array has a layout in which each electrode skips over one or more of the stack structure rows to extend in the third direction.