IP Library Granted Patent US 8,587,076
Granted Patent B2
US 8,587,076 · App. 13/547,913 · Granted Nov 19, 2013

Semiconductor device

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Quick Facts
Patent No.
US 8,587,076
App. No.
13/547,913
Granted
Nov 19, 2013
Kind
B2
Abstract

A semiconductor device includes: a high dielectric constant gate insulating film formed on an active region in a substrate; a gate electrode formed on the high dielectric constant gate insulating film; and an insulating sidewall formed on each side surface of the gate electrode. The high dielectric constant gate insulating film is continuously formed so as to extend from under the gate electrode to under the insulating sidewall. At least part of the high dielectric constant gate insulating film located under the insulating sidewall has a smaller thickness than a thickness of part of the high dielectric constant gate insulating film located under the gate electrode.

Claims (18)

1. A semiconductor device comprising:

a gate insulating film formed on an active region in a substrate and including Hf;

a gate electrode formed on the gate insulating film;

a insulating sidewall formed on each side surface of the gate electrode; and

wherein a width of the gate insulating film along a gate length is larger than a width of the gate electrode along the gate length, and

an end of the gate insulating film under the insulating sidewall is retracted from an outer end of the insulating sidewall toward the gate electrode.

2. The semiconductor device of claim 1 , further comprising a buffer insulating film formed of a silicon oxide film and provided between the substrate and the gate insulating film.

3. The semiconductor device of claim 1 , wherein the gate insulating film is formed of a Hf based oxide.

4. The semiconductor device of claim 1 , wherein the gate insulating film is formed of a HfSiON film.

5. The semiconductor device of claim 1 , wherein a part of the gate insulating film located under the insulating sidewall includes a notch at the end thereof.

6. The semiconductor device of claim 1 , wherein a part of the gate insulating film located under the insulating sidewall has a thickness of 2 nm or less.

7. The semiconductor device of claim 1 , wherein an end of the gate insulating film protrudes from a side end of the gate electrode toward the insulating sidewall.

8. The semiconductor device of claim 1 , wherein the insulating sidewall has a double layer structure including an oxide film and a nitride film.

9. The semiconductor device of claim 1 , wherein the insulating sidewall has a triple layer structure including a first oxide film, a nitride film and a second oxide film.

10. The semiconductor device of claim 1 , wherein a width of a bottom surface of the gate insulating film along a gate length is larger than a width of a bottom surface of the gate electrode along the gate length.

11. The semiconductor device of claim 1 , wherein the end of the gate insulating film located under the insulating sidewall has a tapered surface.

12. The semiconductor device of claim 1 , wherein the gate insulating film located under the insulating sidewall has a thickness which becomes smaller toward the end thereof.

13. The semiconductor device of claim 1 , wherein the width of the gate insulating film along a gate length is larger than a width of part of the gate electrode in a middle position in height along the gate length.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 30, 2024
From: NUVOTON TECHNOLOGY CORPORATION JAPAN
To: ADVANCED INTEGRATED CIRCUIT PROCESS LLC
Reel/Frame 068118/0314 →
CHANGE OF NAME Recorded Jun 12, 2024
From: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
To: NUVOTON TECHNOLOGY CORPORATION JAPAN
Reel/Frame 067711/0965 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC CORPORATION
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0917 →