THIN-FILM TRANSISTOR, ELECTRONIC CIRCUIT, DISPLAY AND METHOD OF MANUFACTURING THE SAME
A bottom gate bottom contact thin-film transistor including a gate electrode, a source electrode, a drain electrode, a dielectric layer and a semiconductor layer of a semiconducting oxide is disclosed. The dielectric layer is arranged between the gate electrode and the semiconductor layer structure, and the source electrode and the drain electrode are covered with said semiconductor layer structure. The source electrode and the drain electrode include at least a first electrode portion of an oxygen reducing material, and a second electrode portion of an additional material different from said oxygen reducing material wherein the second electrode portion of the drain at a side facing the source exposes to said semiconductor layer structure at least a surface portion of a main surface of its first electrode portion facing away from the dielectric layer.
1 . A bottom gate bottom contact thin-film transistor comprising:
a gate electrode;
a source electrode;
a drain electrode;
a dielectric layer; and
a semiconductor layer structure comprising at least one layer of a semiconducting oxide;
wherein said dielectric layer is arranged between said gate electrode and said semiconductor layer, and wherein said source electrode and said drain electrode are covered with said semiconductor layer and separated from each other by semiconducting material within said semiconductor layer,
characterized in that the source electrode and the drain electrode comprise at least a first electrode portion of an oxygen reducing material, and a second electrode portion of an additional material different from said oxygen reducing material, the first electrode portions having a main surface facing away from the dielectric layer, wherein at a side facing the source the main surface of the first electrode portion of the drain has at least a surface portion exposed to said semiconductor layer structure and wherein at a side facing the drain the main surface of the first electrode portion of the source has at least a surface portion exposed to said semiconductor layer structure.
2 . The thin-film transistor according to claim 1 , wherein said additional material has an electric conductivity higher than that of said oxygen reducing material.
3 . The thin-film transistor according to claim 1 , wherein said oxygen reducing material is selected from Ti, Cr, Sn, Zr, V, Fe or an alloy thereof.
4 . The thin-film transistor according to claim 3 , wherein said oxygen reducing material is titanium.
5 . The thin-film transistor of claim 1 , wherein said additional material is selected from Au, W, Mo, MoCr alloy, AlNd alloy, indiumtinoxide (ITO), Al, Cu, Ni.
6 . The thin-film transistor of claim 5 , wherein said additional material is Au.
7 . The thin-film transistor of claim 1 , wherein the first and the second electrode portion are a first and a second layer respectively, and wherein the first layer is arranged between the dielectric layer and the second layer.
8 . The thin-film transistor of claim 7 , wherein a third layer is arranged upon the first layer and the second layer.
9 . The thin-film transistor of claim 8 , wherein the first layer, the second layer and the third layer respectively are a titanium layer, an aluminum layer and a molybdenum layer.
10 . The thin film transistor according to claim 1 , wherein the second electrode portion of at least one of the source electrode and the drain electrode at least partly is in direct contact with the dielectric layer in an area remote from an area where the first electrode portion faces the other one of the source electrode and the drain electrode.
11 . The thin-film transistor of claim 1 , wherein said at least one layer of said semiconducting oxide layer structure comprises indium-gallium-zinc-oxide.
12 . An electronic circuit comprising at least one thin film transistor according to claim 1 .
13 . A display comprising an electronic circuit according to claim 12 , the display having a plurality of display elements controlled by respective driver transistors in the electronic circuit.
14 . A method of manufacturing a bottom gate bottom contact thin film transistor, comprising the sequential steps of:
providing a substrate;
providing a gate metallization;
providing a dielectric layer;
providing a drain and a source; and
providing a semiconductor layer structure comprising at least one layer of a semiconducting oxide over the dielectric layer with the drain and the source,
characterized in that the step of providing a drain and a source comprises:
providing a first electrode portion of an oxygen reducing material; and
providing a second electrode portion of an additional material different from said oxygen reducing material, wherein the first electrode portions has a main surface facing away from the dielectric layer, wherein at a side facing the source the main surface of the first electrode portion of the drain has at least a surface portion exposed to said semiconductor layer structure, and wherein at a side facing the drain the main surface of the first electrode portion of the source has at least a surface portion exposed to said semiconductor layer structure.
15 . The method according to claim 14 , wherein the first and the second electrode portion respectively are provided as a first and a second layer, wherein the second layer is deposited according to a pattern comprising respective, mutually disjunct lateral portions for the drain and the source respectively, and wherein the first layer is deposited blanketwise over these lateral portions, followed by a step of anisotropically etching the first layer in a direction transverse to the substrate.
16 . The method according to claim 14 , wherein the step of providing a drain and a source comprises:
depositing a first layer of said oxygen reducing material;
depositing a second layer of said additional material over the first layer;
applying a resist mask over the second layer having a pattern corresponding to said second portion;
wet etching the second layer; and
dry etching the first layer.
17 . The method of manufacturing an electronic circuit comprising manufacturing at least one bottom gate bottom contact thin film transistor according to the method of one of the claim 14 .
18 . The method according to claim 14 , further including the following steps:
after the step of providing a drain and a source, forming a first and a second electrode, and before the step of providing the semiconductor layer structure, depositing a second dielectric layer, that leaves open a space between the electrodes of the transistor;
depositing a third dielectric layer;
providing a transverse electric connection through the second dielectric layer, the third dielectric layer and the semiconductor layer structure towards one of the first and the second electrodes;
depositing a patterned metal layer having lateral portions that electrically connect with a respective transverse electrical conductor;
depositing a fourth, patterned dielectric layer, having openings that expose the portions of the patterned metal layer;
depositing at least one layer of a light-emitting material; and
depositing a layer of a transparent electrically conductive material forming a cathode.