Variable attenuator having stacked transistors
View Patent ↗In one embodiment, a variable attenuator is disclosed having an attenuation circuit and a control circuit. The attenuation circuit may include a first series connected attenuation circuit segment and a shunt connected attenuation circuit segment, as well as additional attenuation circuit segments. Each attenuation circuit segment includes a stack of transistors that are coupled to provide the attenuation circuit segment with a variable impedance level having a continuous impedance range. In this manner, the control circuit may be operably associated with the stack of transistors in each attenuation circuit segment to control the variable attenuation level of the variable attenuator.
1. An attenuator, comprising:
a silicon-on-insulator type (SOI) substrate having a device layer, a handle layer, and an insulating layer between the device layer and the handle layer;
a first attenuation circuit having a first variable attenuation level that is adjustable within a first continuous attenuation range, wherein:
the first attenuation circuit comprises a first plurality of stacked transistors formed in the device layer of the SOI substrate;
the first plurality of stacked transistors are coupled to provide a first variable impedance level having a first continuous impedance range;
the first variable attenuation level is based on the first variable impedance level;
the insulating layer of the SOI substrate is configured so that an impedance level of a parasitic capacitance of the first plurality of stacked transistors is below the first continuous impedance range; and
a control circuit configured to receive an attenuation control signal, the control circuit being operably associated with the first plurality of stacked transistors to control the first variable impedance level based on a signal level of the attenuation control signal.
2. The attenuator of claim 1 , wherein the insulating layer of the SOI substrate is configured so that the impedance level of the parasitic capacitance of the first plurality of stacked transistors is significantly below the first continuous impedance range whereby the impedance level of the parasitic capacitance is negligible.
3. The attenuator of claim 1 , wherein the parasitic capacitance of the first plurality of stacked transistors is from the device layer to the handle layer.
4. The attenuator of claim 1 , wherein a resistivity of the handle layer is at least 1 kohm-cm.
5. The attenuator of claim 1 , wherein the first attenuation circuit further comprises:
an input terminal;
an output terminal; and
wherein the first plurality of stacked transistors is coupled between the input terminal and the output terminal.
6. The attenuator of claim 5 , wherein the first plurality of stacked transistors is coupled in series with the input terminal or the output terminal.
7. The attenuator of claim 5 , wherein the first plurality of stacked transistors is coupled in shunt between the input terminal and the output terminal.
8. The attenuator of claim 5 , further comprising a second plurality of stacked transistors and wherein:
the second plurality of stacked transistors are coupled to provide a second variable impedance level having a second continuous impedance range;
the second variable attenuation level is further based on the second variable impedance level;
the first plurality of stacked transistors is coupled in series with the input terminal or the output terminal; and
the second plurality of stacked transistors are coupled in shunt between the input terminal and output terminal.
9. The attenuator of claim 8 , wherein the control circuit is operably associated with the second plurality of stacked transistors to control the second variable impedance level based on the signal level of the attenuation control signal.
10. The attenuator of claim 8 , wherein:
the second plurality of stacked transistors are formed in the device layer of the SOI substrate; and
the insulating layer of the SOI substrate is further configured so that an impedance level of a parasitic capacitance of the second plurality of stacked transistors is below the second continuous impedance range.
11. The attenuator of claim 10 , wherein the insulating layer of the SOI substrate is configured so that the impedance level of the parasitic capacitance of the second plurality of stacked transistors is significantly below the second continuous impedance range whereby the impedance level of the parasitic capacitance of the second plurality of stacked transistors is negligible.
12. The attenuator of claim 11 , wherein:
the parasitic capacitance of the first plurality of stacked transistors is from the device layer to the handle layer; and
the parasitic capacitance of the second plurality of stacked transistors is from the device layer to the handle layer.
13. The attenuator of claim 8 , further comprising:
a second SOI substrate having a second device layer, a second handle layer, and a second insulating layer between the second device layer; and
wherein the second plurality of stacked transistors are formed in the second device layer of the second SOI substrate and the second insulating layer of the second SOI substrate is further configured so that an impedance level of a parasitic capacitance of the second plurality of stacked transistors is below the second continuous impedance range.
14. The attenuator of claim 13 , wherein the second insulating layer of the SOI substrate is configured so that the impedance level of the parasitic capacitance of the second plurality of stacked transistors is significantly below the second continuous impedance range whereby the impedance level of the parasitic capacitance of the second plurality of stacked transistors is negligible.
15. The attenuator of claim 14 , wherein:
the parasitic capacitance of the first plurality of stacked transistors is from the device layer to the handle layer; and
the parasitic capacitance of the second plurality of stacked transistors is from the second device layer to the second handle layer.
16. The attenuator of claim 1 , further comprising a variable signal source operable to generate the attenuation control signal that has a variable signal level with a continuous signal range.
17. The attenuator of claim 16 , wherein the variable signal source comprises a variable DC voltage source, the variable signal level being a variable voltage level and the continuous signal range being a continuous voltage range.
18. A method of forming an attenuator, comprising:
providing a handle layer made from a semiconductive material;
selecting a width for each of a plurality of stacked transistors, wherein the width for each of the plurality of stacked transistors is selected so that the plurality of stacked transistor provide a variable impedance level having a continuous impedance range;
providing an insulating layer on the handle layer, wherein the insulating layer is configured so that an impedance level of a parasitic capacitance of the plurality of stacked transistors is below the continuous impedance range; and
providing a device layer over the handle layer such that the device layer is formed to have the plurality of stacked transistors.
19. The method of claim 18 , wherein the insulating layer is configured so that the impedance level of the parasitic capacitance of the first plurality of stacked transistors is significantly below the continuous impedance range whereby the impedance level of the parasitic capacitance is negligible.
20. The method of claim 18 , wherein the parasitic capacitance of the plurality of stacked transistors is from the device layer to the handle layer.