Memory device and method of manufacturing the same

1. A memory device comprising:

a plurality of memory elements, each memory element having a first electrode, a second electrode, and a memory layer between the first electrode and the second electrode; and

a plurality of access transistors operatively connected to the plurality of memory elements and controlled by a plurality of word lines,

wherein,

a plurality of memory layers provided for the plurality of memory elements are in a dotlike pattern,

two adjacent first electrodes from corresponding two adjacent memory elements share one memory layer,

the one memory layer fills a hole in an insulating film provided over the two adjacent first electrodes, the hole exposing the two adjacent first electrodes and being filled with the one memory layer, and

the one memory layer extends over the two adjacent first electrodes in a direction parallel to an extension direction of the plurality of word lines.

2. The memory device of claim 1 further comprising:

a plurality of bit lines including first bit lines and second bit lines,

wherein,

the two adjacent first electrodes are connected to one first bit line through corresponding two adjacent access transistors, and

two memory layers adjacent to each other in a direction perpendicular to the extension direction of the plurality of word lines are connected to one second bit line.

3. The memory device of claim 2 , wherein:

one of a source and a drain of each access transistor is connected to a corresponding first bit line through a bit contact electrode, and

the other one of the source and the drain of the access transistor is connected to a corresponding first electrode through a node contact electrode.

4. The memory device of claim 3 , wherein:

one bit contact electrode is shared by two adjacent access transistors, and

one node contact electrode is provided for each access transistor.

5. The memory device of claim 2 , wherein the second bit line functions as the second electrode.

6. The memory device of claim 2 , wherein potentials applied to both the first bit line and the second bit line change between a positive potential and a ground potential in a complementary manner, such that a positive voltage or a negative voltage is applied to each memory layer.

7. The memory device of claim 2 , wherein:

a width of each word line and each first bit line is equal to a minimum dimension rule,

a pitch of the first bit lines is three times greater than the minimum dimension rule, and

a pitch of the word lines is twice greater than the minimum dimension rule.

8. The memory device of claim 1 , wherein:

each memory layer comprises a resistance change layer and an ion source layer,

the ion source layer includes at least one chalcogen element as an anodic ion conducive material and at least one metal element as a cationic element, and

the resistance change layer is made of a material having a resistance value greater than that of the ion source layer and has a function of an electrical conductive barrier.

9. The memory device of claim 1 , wherein:

each memory element is a phase change memory, and

each memory layer is made of a GeSbTe alloy.

10. The memory device of claim 1 , wherein:

each memory element is a resistive change memory, and

each memory layer is made of an oxide.

11. The memory device of claim 2 , wherein the second bit line is disposed in parallel to the first bit line.

12. A method for manufacturing a memory device, comprising:

forming a plurality of memory elements on a semiconductor substrate, each memory element having a first electrode, a second electrode, and a memory layer between the first electrode and the second electrode;

forming a plurality of access transistors on the semiconductor substrate; and

connecting a plurality of word lines to the plurality of access transistors,

wherein,

a plurality of memory layers formed for the plurality of memory elements are in a dotlike pattern,

two adjacent first electrodes from corresponding two adjacent memory elements share one memory layer,

the one memory layer fills a hole in an insulating film formed over the two adjacent first electrodes, the hole exposing the two adjacent first electrodes and being filled with the one memory layer, and

the one memory layer extends over the two adjacent first electrodes in a direction parallel to an extension direction of the plurality of word lines.

13. The method of claim 12 , further comprising:

forming a plurality of bit lines including first bit lines and second bit lines on the semiconductor substrate,

wherein,

the two adjacent first electrodes are connected to one first bit line through corresponding two adjacent access transistors, and

two memory layers adjacent to each other in a direction perpendicular to the extension direction of the plurality of word lines are connected to one second bit line.

14. The method of claim 13 , further comprising:

connecting a bit contact electrode to each access transistor;

connecting the first bit line to the bit contact electrode;

connecting a node contact electrode to each access transistor; and

forming a corresponding first electrode on the node contact electrode.

15. The method of claim 12 , wherein forming the plurality of memory elements includes:

covering an upper portion of the first electrode of each memory element with the insulating film;

forming the hole in the insulating film to expose the two adjacent first electrodes;

filling the hole with a memory layer material film to form the one memory layer shared by the two adjacent first electrodes; and

removing the memory layer material film extruded from the hole by chemical mechanical polishing.

16. The method of claim 13 , further comprising:

forming another insulating film on each memory layer; and

connecting a respective second bit line to a corresponding memory layer through a contact hole in the other insulating film.

17. The method of claim 13 , wherein:

a width of each word line and each first bit line is equal to a minimum dimension rule,

a pitch of the first bit lines is three times greater than the minimum dimension rule, and

a pitch of the word lines is twice greater than the minimum dimension rule.

18. The method of claim 12 , wherein:

each memory layer comprises a resistance change layer and an ion source layer,

the ion source layer includes at least one chalcogen element as an anodic ion conducive material and at least one metal element as a cationic element, and

the resistance change layer is made of a material having a resistance value greater than that of the ion source layer and has a function as an electrical conductive barrier.

19. A memory system comprising:

a memory interface;

a memory device comprising

(a) a plurality of memory elements, each memory element having a first electrode, a second electrode, and a memory layer between the first electrode and the second electrode, and

(b) a plurality of access transistors operatively connected to the plurality of memory elements and controlled by a plurality of word lines; and

(c) a memory controller operatively connected to the memory interface and the memory device, and configured to control operations of the memory device,

wherein,

a plurality of memory layers provided for the plurality of memory elements are in a dotlike pattern,

two adjacent first electrodes from corresponding two adjacent memory elements share one memory layer,

the one memory layer fills a hole in an insulating film provided over the two adjacent first electrodes, the hole exposing the two adjacent first electrodes and being filled with the one memory layer, and

the one memory layer extends over the two adjacent first electrodes in a direction parallel to an extension direction of the plurality of word lines.