Memory module and layout method therefor
View Patent ↗The present invention provides a novel wiring method for LR-DIMM of VLP type that conforms to LR-DIMM technology. The LR-DIMM comprises a plurality of DRAMs mounted on a board, two connectors mounted on the board for receiving data, and a buffer device mounted on the board for redriving data applied to the two connectors to supply the data to the plurality of DRAMs. The buffer device is located near the center of the board on which the two connectors are arranged at both ends thereof, and supplies data from each connector to DRAMs arranged on the opposite side to the connector.
1. A memory module, comprising:
a printed circuit board (PCB) of a rectangular shape defined by first and second short sides opposite to each other, and first and second long sides opposite to each other, the module substrate including a first region defined by the first and second long sides and the first short side, a second region defined by the first and second long sides and the second short side and a third region defined between the first and second regions;
a first set of memory devices provided on the first region of the PCB;
a second set of memory devices provided on the second region of the PCB;
a first buffer device provided on the third region of the PCB;
a second buffer device provided on the third region of the PCB;
a first set of terminals provided on the first region of the PCB, between the first long side and the first set of memory devices;
a second set of terminals provided on the second region of the PCB, between the first long side and the second set of memory devices;
a third set of terminals provided on the third region of the PCB, between the first and second sets of terminals;
a first group of wires provided between the first set of terminals and the first buffer device to transfer a first data therebetween;
a second group of wires provided between the second set of terminals and the second buffer device to transfer a second data therebetween:
a third group of wires provided between the first and second buffer devices;
a fourth group of wires provided between the third group of wires and the third set of terminals to transfer a command signal, an address signal, a control signal and a clock signal therebetween;
a fifth group of wires provided between the first buffer and the second set of memory devices; and
a sixth group of wires provided between the second buffer device and the first set of memory devices.
2. The memory module as claimed in claim 1 ,
wherein the PCB includes a first main surface and a second main surface;
wherein the first buffer device is provided on the first main surface and the second buffer is provided on the second main surface.
3. The memory module as claimed in claim 2 ,
wherein the first buffer device overlaps the second buffer device.
4. The memory module as claimed in claim 1 ,
wherein the PCB includes a first main surface and a second main surface;
wherein the first and second buffer devices are provided on the first main
surface.
5. The memory module as claimed in claim 4 ,
wherein the first and second buffer devices are arranged in series between the first and second long sides.
6. The memory module as claimed in claim 1 , further comprising:
a first termination resistor provided between the first short side and a memory device located adjacent to the first short side among the first set of memory devices and connected to the sixth group of wires, and
a second termination resistor provided between the second short side and a memory device located adjacent to the second short side among the second set of memory devices and connected to the fifth group of wires.
7. The memory module as claimed in claim 1 ,
wherein the fifth set of wires includes a set of first data wires to transfer the first data between the first buffer device and the second set of memory devices;
wherein the sixth set of wires includes a set of second data wires to transfer the second data between the second buffer device and the first set of memory devices; and
wherein a number of the first wires and first data wires is identical to a number of the second wires and second data wires.
8. The memory module as claimed in claim 1 ,
wherein the memory module is a load reduce dual inline memory module (LR-DIMM).
9. The memory module as claimed in claim 8 ,
wherein the LR-DIMM is a very low profile (VLP) type.
10. A memory module, comprising:
a module substrate of a rectangular shape defined by first and second short sides opposite to each other, and first and second long sides opposite to each other, the module substrate including a first region defined by the first and second long sides and the first short side, a second region defined by the first and second long sides and the second short side;
a first set of memory devices provided on the first region of the module substrate;
a second set of memory devices provided on the second region of the module substrate;
a first buffer device provided on the module substrate;
a second buffer device provided on the module substrate;
a first set of terminals provided on the first region of the module substrate, between the first long side and the first set of memory devices;
a second set of terminals provided on the second region of the module substrate, between the first long side and the second set of memory devices;
a first group of wires provided between the first set of terminals and the first buffer device to transfer a first data therebetween;
a second group of wires provided between the second set of terminals and the second buffer device to transfer a second data therebetween;
a third group of wires provided between the first buffer device and the second set of memory devices to transfer the first data therebetween; and
a fourth group of wires provided between the second buffer device and the first set of memory devices to transfer the second data therebetween.
11. The memory module as claimed in claim 10 , further comprising:
a third set of terminals provided on the third region of the module substrate, between the first and second sets of terminals;
a fifth group of wires provided between the first and second buffer devices;
a sixth group of wires provided between the fifth group of wires and the third set of terminals to transfer at least one of a command signal, an address signal, a control signal and a clock signal therebetween;
a seventh group of wires provided between the first buffer device and the second set of memory devices to transfer at least the one therebetween; and
an eighth group of wires provided between the second buffer device and the first set of memory devices to transfer at least the one therebetween.
12. The memory module as claimed in claim 10 ,
wherein the module substrate includes a first main surface and a second main surface;
wherein the first buffer device is provided on the first main surface and the second buffer device is provided on the second main surface.
13. The memory module as claimed in claim 10 ,
wherein the module substrate includes a first main surface and a second main surface;
wherein the first and second buffer devices are provided on the first main surface.
14. The memory module as claimed in claim 11 , further comprising:
a first termination resistor provided between the first short side and a memory device located adjacent to the first short side among the first set of memory devices and connected to the eighth group of wires, and
a second termination resistor provided between the second short side and a memory device located adjacent to the second short side among the second set of memory devices and connected to the seventh group of wires.
15. The memory module as claimed in claim 10 ,
wherein a number of the first wires and fourth wires is identical to a number of the second wires and third wires.
16. The memory module as claimed in claim 10 ,
wherein the memory module is a load reduce dual inline memory module of a very low profile type.
17. A memory module, comprising:
a module substrate of a rectangular shape defined by first and second short sides opposite to each other, and first and second long sides opposite to each other, the module substrate including a first region defined by the first and second long sides and the first short side, a second region defined by the first and second long sides and the second short side;
a first set of memory devices provided on the first region of the module substrate;
a second set of memory devices provided on the second region of the module substrate;
a first buffer device provided on the module substrate;
a second buffer device provided on the module substrate;
a set of terminals provided on the module substrate to receive at least one of a command signal, an address signal, a command signal and a clock signal;
a first group of wires provided between the first and second buffer devices;
a second group of wires provided between the first group of wires and the set of terminals;
a third group of wires provided between the first buffer device and the second set of memory devices to transfer at least the one therebetween; and
an fourth group of wires provided between the second buffer device and the first set of memory devices to transfer at least the one therebetween.
18. The memory module as claimed in claim 17 ,
wherein the module substrate includes a first main surface and a second main surface;
wherein the first buffer device is provided on the first main surface and the second buffer is provided on the second main surface.
19. The memory module as claimed in claim 17 ,
wherein the module substrate includes a first main surface and a second main surface;
wherein the first and second buffer devices are provided on the first main surface.
20. The memory module as claimed in claim 17 ,
wherein the memory module is a load reduce dual inline memory module of a very low profile type.