SHALLOW-TRENCH CMOS-COMPATIBLE SUPER JUNCTION DEVICE STRUCTURE FOR LOW AND MEDIUM VOLTAGE POWER MANAGEMENT APPLICATIONS
A novel lateral super junction device compatible with standard CMOS processing techniques using shallow trench isolation is provided for low- and medium-voltage power management applications. The concept is similar to other lateral super junction devices having N- and P-type implants to deplete laterally to sustain the voltage. However, the use of shallow trench structures provides the additional advantage of reducing the Rdson without the loss of the super junction concept and, in addition, increasing the effective channel width of the device to form a “FINFET” type structure, in which the conducting channel is wrapped around a thin silicon “fin” that forms the body of the device. The device is manufactured using standard CMOS processing techniques with the addition of super junction implantation steps, and the addition of polysilicon within the shallow trench structures to form fin structures.
1 - 14 . (canceled)
15 . A method of manufacturing a shallow trench super junction LDMOS semiconductor device in a silicon substrate, comprising the steps of:
etching a plurality of shallow trenches within the silicon substrate;
implanting a P-type super junction region in the silicon substrate at a base of each of the plurality of shallow trenches;
growing an oxide layer that at least partially fills the plurality of shallow trenches within the silicon substrate;
implanting an N-drift super junction layer in the silicon substrate between the plurality of shallow trenches and adjacent to each of the P-type super junction regions at the base of each of the plurality of shallow trenches;
masking the oxide layer to cover at least a portion of the oxide layer that at least partially fills the plurality of shallow trenches within the silicon substrate;
etching the oxide layer to remove at least a portion of the oxide layer that is not covered in the masking step;
growing an additional oxide layer configured as a gate oxide;
depositing a polysilicon layer such that it at least partially fills the plurality of trenches and also covers the additional oxide layer to form a gate electrode;
forming a source contact adjacent to a first side of the polysilicon gate electrode; and
forming a drain contact on a second side of the polysilicon gate electrode opposite from the source electrode.
16 . The method of manufacturing a shallow trench super junction LDMOS semiconductor device in a silicon substrate of claim 15 , wherein the step of growing an additional oxide layer further comprises growing oxide within the plurality of shallow trenches.
17 . The method of manufacturing a shallow trench super junction LDMOS semiconductor device in a silicon substrate of claim 15 , wherein the plurality of shallow trenches comprises two shallow trenches.
18 . The method of manufacturing a shallow trench super junction LDMOS semiconductor device in a silicon substrate of claim 15 , wherein the process of etching a plurality of shallow trenches within the silicon substrate comprising etching the plurality of shallow trenches to a depth of approximately 0.4 micrometers.
19 . The method of manufacturing a shallow trench super junction LDMOS semiconductor device in a silicon substrate of claim 15 , wherein the process of etching a plurality of shallow trenches within the silicon substrate comprising etching the plurality of shallow trenches such that they are spaced by approximately 0.6 micrometers.
20 . The method of manufacturing a shallow trench super junction LDMOS semiconductor device in a silicon substrate of claim 15 , wherein the process of growing an oxide layer that at least partially fills the plurality of shallow trenches within the silicon substrate further comprises growing an additional field oxide region adjacent to the oxide layer that at least partially fills the plurality of shallow trenches.
21 . The method of manufacturing a shallow trench super junction LDMOS semiconductor device in a silicon substrate of claim 20 , further comprising depositing a polysilicon layer such that it forms a polysilicon field plate above the additional field oxide region located adjacent to the oxide layer that at least partially fills the plurality of shallow trenches.