Systems and methods for channel target based CBD estimation
Various approaches, methods, systems, circuits and devices for channel bit density estimation.
1. A data processing system, the system comprising:
a channel bit density estimation circuit operable to:
receive a pulse derived from a channel exhibiting a first sample rate;
up-sample the pulse at a second sample rate to yield an up-sampled pulse;
calculate a first estimated channel bit density of the channel based on the up-sampled pulse; and
add a fixed offset to the first channel bit density to yield a second channel bit density.
2. The data processing system of claim 1 , wherein calculating the estimated channel bit density comprises:
determining a width of the pulse corresponding to approximately one half of a peak value of the up-sampled pulse; and
calculating the estimated channel bit density based on the width.
3. The data processing system of claim 1 , wherein the second sample rate is an integer multiple of the first sample rate.
4. The data processing system of claim 1 , wherein the fixed offset corresponds to a calibrated difference between the first estimated channel bit density and an actual channel bit density.
5. The data processing system of claim 1 , wherein the data processing system is implemented as part of a storage device, and wherein the channel includes a storage medium.
6. The data processing system of claim 1 , wherein the data processing system is implemented as part of a communication device, and wherein the channel includes a communication medium.
7. The data processing system of claim 1 , wherein the data processing system is implemented as part of an integrated circuit.
8. A method for channel bit density estimation, the method comprising:
receiving a pulse derived from a channel exhibiting a first sample rate;
up-sampling the pulse at a second sample rate to yield an up-sampled pulse; and
calculating a first estimated channel bit density of the channel based on the up-sampled pulse; and
adding a fixed offset to the first channel bit density to yield a second channel bit density.
9. The method of claim 8 , wherein calculating the estimated channel bit density comprises:
determining a width of the pulse corresponding to approximately one half of a peak value of the up-sampled pulse; and
calculating the estimated channel bit density based on the width.
10. The method of claim 8 wherein the second sample rate is an integer multiple of the first sample rate.
11. A data storage device, the device comprising:
a storage medium;
a read/write head assembly operable to sense information from the storage medium and to provide a corresponding continuous signal;
an analog to digital converter circuit operable to sample the continuous signal synchronous to a sampling clock to yield a set of digital samples;
a channel bit density estimation circuit operable to:
receive a Dibit pulse derived from a channel including the storage medium exhibiting a first sample rate;
up-sample the Dibit pulse at a second sample rate to yield an up-sampled pulse;
calculate a first estimated channel bit density of the channel based on the up-sampled pulse; and
add a fixed offset to the first channel bit density to yield a second channel bit density.
12. The device of claim 11 , wherein calculating the estimated channel bit density comprises:
determining a width of the Dibit pulse corresponding to approximately one half of a peak value of the up-sampled pulse; and
calculating the estimated channel bit density based on the width.
13. The device of claim 11 , wherein the second sample rate is an integer multiple of the first sample rate.
14. The device of claim 11 , wherein the fixed offset corresponds to a calibrated difference between the first estimated channel bit density and an actual channel bit density.
15. The device of claim 11 , wherein the storage medium is a magnetic medium.
16. A data communication device, the device comprising:
a receiver operable to:
receive information from a communication medium; and
provide a continuous signal corresponding to the information;
an analog to digital converter circuit operable to sample the continuous signal synchronous to a sampling clock to yield a set of digital samples;
a channel bit density estimation circuit operable to:
receive a Dibit pulse derived from a channel including the communication medium exhibiting a first sample rate;
up-sample the Dibit pulse at a second sample rate to yield an up-sampled pulse;
calculate a first estimated channel bit density of the channel based on the up-sampled pulse; and
adding a fixed offset to the first channel bit density to yield a second channel bit density.
17. The device of claim 16 , wherein calculating the estimated channel bit density comprises:
determining a width of the Dibit pulse corresponding to approximately one half of a peak value of the up-sampled pulse; and
calculating the estimated channel bit density based on the width.
18. The device of claim 16 , wherein the second sample rate is an integer multiple of the first sample rate.
19. The device of claim 16 , wherein the fixed offset corresponds to a calibrated difference between the first estimated channel bit density and an actual channel bit density.
20. The storage device of claim 11 , wherein the channel bit density estimation circuit is implemented as part of an integrated circuit.
21. The storage device of claim 11 , wherein the channel bit density estimation circuit and the analog to digital converter circuit are implemented as part of an integrated circuit.
22. The communication device of claim 16 , wherein the channel bit density estimation circuit is implemented as part of an integrated circuit.