Compensation for lane imbalance in a multi-lane analog-to-digital converter (ADC)

1. A multi-lane analog to digital converter (ADC) for converting an analog input from an analog signal domain to a digital signal domain to provide digital output samples, comprising:

a plurality of ADCs configured to:

convert the analog input from the analog signal domain to the digital signal domain to provide a first plurality of digital output segments in a first mode of operation, each of the plurality of ADCs being configured to sample the analog input using a corresponding phase from among multiple phases of a sampling clock, the multiple phases being offset from each other, and

convert a calibration signal from the analog signal domain to the digital signal domain to provide a second plurality of digital output segments in a second mode of operation, each of the plurality of ADCs being configured to sample the calibration signal using the corresponding phase from among the multiple phases of the sampling clock;

a switching module configured to interleave the first plurality of digital output segments to provide the digital output samples; and

an impairment detection module configured to:

generate the calibration signal having a known characteristic in the second mode of operation, and

determine statistical relationships between the second plurality of digital output segments and the calibration signal to quantify impairments induced by the plurality of ADCs on the first plurality of digital output segments.

2. The multi-lane ADC of claim 1 , wherein the statistical relationships are correlations between the second plurality of digital output segments and the calibration signal.

3. The multi-lane ADC of claim 1 , wherein the impairments comprise:

phase offsets between phases from among the multiple phases and the calibration signal;

amplitude offsets between the second plurality of digital output segments and the calibration signal; or

direct current (DC) offsets between the second plurality of digital output segments and the calibration signal.

4. The multi-lane ADC of claim 1 , wherein the calibration signal is a sinusoidal signal having a known frequency.

5. The multi-lane ADC of claim 1 , wherein the impairment detection module is further configured to provide a plurality of impairment correction signals based upon the statistical relationships, and further comprising:

a phase adjustment module configured to adjust a phase of one of the multiple phases based upon a corresponding first one of the plurality of impairment correction signals; and

a gain/offset adjustment module configured to adjust an amplitude and a direct current (DC) offset of one of the first plurality of digital output segments based upon a corresponding second one of the plurality of impairment correction signals.

6. The multi-lane ADC of claim 1 , wherein the impairment detection module is further configured to provide a plurality of impairment correction signals based upon the statistical relationships, and further comprising:

a coefficient generator module configured to provide a plurality of sets of correction coefficients based upon the plurality of impairment correction signals; and

a plurality of tapped delay line modules, coupled to the plurality of ADCs, configured to compensate for the impairments within the first plurality of digital output segments by weighting their corresponding taps using corresponding sets of correction coefficients from among the plurality of sets of correction coefficients to provide a plurality of compensated digital output segments,

wherein the switching module is further configured to interleave the plurality of compensated digital output segments to provide the digital output samples.

7. The multi-lane ADC of claim 6 , wherein the coefficient generator module is further configured to update the plurality of sets of correction coefficients using an adaptive algorithm that yields a result which minimizes errors between the second plurality of digital output segments and the calibration signal.

8. The multi-lane ADC of claim 1 , wherein the impairment detection module is further configured to assign one of the second plurality of digital output segments as a reference lane and to compare the statistical relationships of the other digital output segments from among the second plurality of digital output segments to a statistical relationship of the reference lane to quantify the impairments of the other digital output segments relative to the reference lane.

9. The multi-lane ADC of claim 8 , wherein the statistical relationships are correlations between the second plurality of digital output segments and the calibration signal.

10. A multi-lane analog to digital converter (ADC) for converting an analog input from an analog signal domain to a digital signal domain to provide digital output samples, comprising:

a plurality of ADCs configured to:

convert the analog input from the analog signal domain to the digital signal domain to provide a first plurality of digital output segments in a first mode of operation, each of the plurality of ADCs being configured to sample the analog input using a corresponding phase from among multiple phases of a sampling clock, the multiple phases being offset from each other, and

convert a calibration signal from the analog signal domain to the digital signal domain to provide a second plurality of digital output segments in a second mode of operation, each of the plurality of ADCs being configured to sample the calibration signal using the corresponding phase from among the multiple phases of the sampling clock;

an impairment detection module configured to:

generate the calibration signal having a known amplitude, a known direct current (DC) offset, or a known phase, and

determine statistical relationships between the second plurality of digital output segments and a plurality of frequencies of the calibration signal to quantify impairments induced by the plurality of ADCs on the first plurality of digital output segments;

a coefficient generator module configured to provide a plurality of sets of correction coefficients based upon the statistical relationships;

a plurality of tapped delay line modules, coupled to the plurality of ADCs, configured to compensate for the impairments by weighting their corresponding taps using corresponding sets of correction coefficients from among the plurality of sets of correction coefficients to provide a plurality of compensated digital output segments; and

a switching module configured to interleave the plurality of compensated digital output segments to provide the digital output samples.

11. The multi-lane ADC of claim 10 , wherein the statistical relationships are correlations between the second plurality of digital output segments and the calibration signal.

12. The multi-lane ADC of claim 10 , wherein the impairment detection module is further configured to determine the statistical relationships between the second plurality of digital output segments and the calibration signal to quantify the impairments within the first plurality of digital output segments.

13. The multi-lane ADC of claim 12 , wherein the impairment detection module is further configured to:

assign one of the second plurality of digital output segments as a reference lane, and

compare the statistical relationships for the other digital output segments from among the second plurality of digital output segments to a statistical relationship of the reference lane to quantify the impairments of the other digital output segments relative to the reference lane.

14. The multi-lane ADC of claim 13 , wherein the statistical relationships are correlations between the second plurality of digital output segments and the calibration signal.

15. The multi-lane ADC of claim 10 , wherein the impairments comprise:

phase offsets between phases from among the multiple phases and the calibration signal; or

amplitude offsets between the second plurality of digital output segments and the calibration signal.

16. The multi-lane ADC of claim 10 , further comprising:

an offset detection module configured to determine a DC offset between the second plurality of digital output segments and the calibration signal to provide a plurality of DC offset signals; and

a plurality of combination modules configured to combine the second plurality of digital output segments with the plurality of DC offset signals to provide a plurality of offset corrected output segments,

wherein the plurality of tapped delay line modules are further configured to compensate for impairments within the plurality of offset corrected output segments.

17. The multi-lane ADC of claim 10 , wherein the plurality of tapped delay line modules are implemented as part of a plurality of adaptive equalizers, the plurality of adaptive equalizers being configured to compensate for the impairments within the second plurality of digital output segments by adjusting their impulse responses using the plurality of sets of correction coefficients.

18. A multi-lane analog to digital converter (ADC) configured for converting an analog input from an analog signal domain to a digital signal domain to provide digital output samples, comprising:

a plurality of ADCs configured to:

convert the analog input from the analog signal domain to the digital signal domain to provide a first plurality of digital output segments in a first mode of operation, each of the plurality of ADCs being configured to sample the analog input using a corresponding phase from among multiple phases of a sampling clock, the multiple phases being offset from each other, and

convert a calibration signal from the analog signal domain to the digital signal domain to provide a second plurality of digital output segments in a second mode of operation, each of the plurality of ADCs being configured to sample the calibration signal using the corresponding phase from among, the multiple phases of the sampling clock;

an impairment detection module configured to:

generate the calibration signal having a known amplitude, a known direct current (DC) offset, or a known phase, and

determine statistical relationships between the second plurality of digital output segments and the calibration signal to quantify impairments induced by the plurality of ADCs on the first plurality of digital output segments;

a plurality of phase adjustment modules configured to adjust phases of the multiple phases based upon the statistical relationships to compensate for the impairments;

a plurality of gain/offset adjustment modules, coupled to the plurality of ADCs, configured to adjust amplitudes and direct current (DC) offsets of the first plurality of digital output segments based upon the statistical relationships to provide a plurality of compensated digital output segments; and

a switching module configured to interleave the plurality of compensated digital output segments to provide the digital output samples.

19. The multi-lane ADC of claim 18 , wherein the statistical relationships are correlations between the second plurality of digital output segments and the calibration signal.

20. The multi-lane ADC of claim 18 , wherein the impairment detection module is further configured to assign one of the second plurality of digital output segments as a reference lane and to compare the statistical relationships of the other digital output segments from among the second plurality of digital output segments to a statistical relationship of the reference lane to quantify the impairments of the other digital output segments relative to the reference lane.

21. The multi-lane ADC of claim 18 , wherein the impairments comprise:

phase offsets between the multiple phases and the calibration signal;

amplitude offsets between the second plurality of digital output segments and the calibration signal; or

DC offsets between the second plurality of digital output segments and the calibration signal.

22. The multi-lane ADC of claim 1 , wherein the known characteristic comprises:

a known amplitude;

a known direct current (DC) offset; or

a known phase.

23. The multi-lane ADC of claim 1 , wherein the calibration signal is characterized as having a single frequency to quantify the impairments present within the single frequency.

24. The multi-lane ADC of claim 1 , wherein the calibration signal is characterized as having multiple frequencies to quantify the impairments present within the multiple frequencies.

25. The multi-lane ADC of claim 1 , further comprising:

a second switching module configured to select the analog input to be converted by the plurality of ADCs in the first mode of operation or the calibration signal to be converted by the plurality of ADCs in the second mode of operation.

26. The multi-lane ADC of claim 1 , wherein the first mode of operation is a normal mode of operation, and

wherein the second mode of operation is a calibration mode of operation.

27. The multi-lane ADC of claim 1 , wherein the impairment detection module is further configured to provide a plurality of impairment correction signals based upon the statistical relationships, and further comprising:

a phase adjustment module configured to adjust a phase of one of the multiple phases based upon a corresponding first one of the plurality of impairment correction signals; and

a gain/offset adjustment module configured to adjust an amplitude and a direct current (DC) offset of one of the first plurality of digital output segments in the first mode of operation or one of the second plurality of digital output segments in the second mode of operation based upon a corresponding one of the plurality of impairment correction signals.