PROTECTION OF UNDER-LAYER CONDUCTIVE PATHWAY
Systems and methods are presented for preventing removal of material comprising a metal gate during removal of a mask layer in a semiconductor structure. Upon exposure of the metal line during formation of a via opening the exposed portion of the metal line undergoes chemical modification to form a passivation layer. The passivation layer is subsequently covered by an etch selectivity layer, wherein the etch selectivity layer prevents removal of at least one of a portion of the metal line or the passivation layer during removal of a hard mask layer comprising the semiconductor structure. In an alternate approach, the metal line is formed with a capping layer which, following exposure by a via opening formed in the semiconductor structure, is chemically modified to form a layer having etch selectivity to acts as a protective layer during removal of a hard mask layer comprising the semiconductor layer.
1 . A semiconductor structure, comprising:
a plurality of layers including a mask layer;
a via opening through the plurality of layers including the mask layer;
a metal line, wherein a surface of the metal line is exposed by the via opening;
a passivation layer, wherein the passivation layer is formed from a portion of the metal line exposed by the via opening; and
an etch selectivity layer, wherein the etch selectivity layer is formed on the passivation layer.
2 . The semiconductor of claim 1 , wherein the passivation layer comprises a silicide formed by chemical modification of a portion of the metal line exposed by the via opening.
3 . The semiconductor of claim 1 , wherein the metal line comprises copper.
4 . The semiconductor of claim 1 , wherein the passivation layer comprises copper silicide formed by chemical modification of a portion of the metal line.
5 . The semiconductor of claim 1 , wherein the etch selectivity layer comprises an oxide.
6 . The semiconductor of claim 1 , wherein the etch selectivity layer comprises silicon oxide.
7 . The semiconductor of claim 1 , wherein the etch selectivity layer protects at least one of a portion of the passivation layer or a portion of the metal line during removal of the mask layer.
8 . The semiconductor of claim 1 , wherein in the event of removal of at least the mask layer the via opening is filled with conductive material to form an interconnect.
9 . The semiconductor of claim 8 , wherein the interconnect connects with the passivation layer exposed by removal of the etch selectivity layer.
10 . A method for forming a semiconductor device, comprising:
forming a semiconductor stack comprising a metal line and a plurality of layers including a mask layer;
forming a via in the semiconductor stack exposing a surface of the metal line;
converting a portion of the exposed surface of the metal line to form a passivation layer; and
forming a protective layer on the passivation layer.
11 . The method of claim 10 , wherein the metal line comprises copper.
12 . The method of claim 10 , wherein the passivation layer comprises a silicide.
13 . The method of claim 10 , wherein the passivation layer comprises copper silicide.
14 . The method of claim 10 , wherein the protective layer comprises an oxide.
15 . The method of claim 10 , further comprising removing the mask layer, whereby the protective layer preventing removal of at least one of a portion of the passivation layer or a portion of the metal line.
16 . The method of claim 15 , further comprising, in the event of removal of at least the mask layer the via opening is filled with conductive material to form an interconnect.
17 . The method of claim 16 , wherein the interconnect connecting with the passivation layer exposed by removing the etch selectivity layer.
18 . A semiconductor structure, comprising:
a plurality of layers including a mask layer;
a via opening formed through the plurality of layers including the mask layer;
a metal line located in a layer comprising the plurality of layers, wherein the metal line further comprising a capping layer, the capping layer is exposed by the via opening.
19 . The semiconductor structure of claim 18 , wherein the capping layer is chemically modified to comprise material having etch selectivity to an etch utilized to subsequently remove the mask layer.
20 . The semiconductor structure of claim 18 , wherein the metal layer comprises copper, and the capping layer comprises manganese.