IP Library Granted Patent US 8,599,997
Granted Patent B2
US 8,599,997 · App. 13/556,392 · Granted Dec 3, 2013

Multiple-modulus divider and associated control method

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Quick Facts
Patent No.
US 8,599,997
App. No.
13/556,392
Granted
Dec 3, 2013
Kind
B2
Abstract

A multiple-modulus divider and an associated control method are provided. The multiple-modulus divider includes a divisor loader, a multiple-modulus dividing circuit and a modulus controller. The divisor loader downloads a divisor when a download signal indicates a start of a division period. The multiple-modulus circuit includes a plurality of cascaded divisors, and provides an output frequency according to an input frequency and the divisor. The dividers respectively output a plurality of modulus output signals, and each is operable under either a close-loop state or an open-loop state. The modulus controller selects and controls one of the dividers according to the divisor, and ensures the selected divider is maintained at the open-loop state when the division period ends. The download signal corresponds to one of the modulus output signals.

Claims (25)

1. A multiple-modulus divider, comprising:

a divisor loader, for downloading a divisor when a download signal indicates a start of a divisor period;

a multiple-modulus dividing circuit, comprising a plurality of cascaded dividers, for providing an output frequency according to an input frequency and the divisor, with each divider respectively outputting a plurality of modulus output signals and operating under either a close-loop state or an open-loop state; and

a modulus controller, for selectively controlling one of the dividers to maintain the open-loop state before the divisor period ends;

wherein, the download signal is generated according to the modulus output signals.

2. The multiple-modulus divider according to claim 1 , wherein the divisor loader downloads the divisor at a first switching edge of the download signal, and the modulus controller controls the selected divider at a second switching edge of the download signal.

3. The multiple-modulus divider according to claim 1 , wherein the divisor is operable to cause a first number of dividers to perform frequency dividing to generate the output frequency, and the download signal is outputted by a last divider of the first number of dividers.

4. The multiple-modulus divider according to claim 3 , wherein the last divider comprises a D latch for outputting one of the modulus signals, and the modulus controller and the download signal are capable of controlling a D input of the D latch.

5. The multiple-modulus divider according to claim 3 , wherein the selected divider is a next divider of the first number dividers.

6. The multiple-modulus divider according to claim 1 , wherein the selected divider comprises a D latch for outputting one of the modulus signals, and the modulus controller controls a D input of the D latch.

7. The multiple-modulus divider according to claim 1 , a first divider divides a frequency by two when the divider operates under the close-loop state.

8. A control method of modulus frequency dividing for a multiple-modulus dividing circuit, the multiple-modulus dividing circuit comprising a plurality of cascaded dividers and outputting an output frequency according to an input frequency and a divisor, each divider being operable under either a close-loop state or an open-loop state, the method comprising:

providing a download signal for indicating a division period;

loading the divisor in response to the download signal;

selecting one of the dividers as a selected divider according to the divisor; and

enabling the selected divider to operate under the open-loop state during the division period in response to the download signal.

9. The control method according to claim 8 , further comprising:

a first number of dividers of the dividers performing frequency dividing according to the divisor to generate the output frequency;

wherein, the download signal is provided by a last divider of the first number of dividers.

10. The control method according to claim 9 , wherein the selected divider is a next divider of the first number dividers.

11. The control method according to claim 9 , the last divider of the first number of dividers comprising a D latch, the D latch comprising a D input and outputting a modulus signal, the method further comprising:

providing the download signal according to the modulus signal.

12. The control method according to claim 9 , the last divider of the first number of dividers comprising a D latch, the D latch comprising a D input and outputting a modulus signal, the method further comprising:

controlling the D input according to the download signal.

13. The control method according to claim 8 , the last divider of the first number of dividers comprising a D latch, the D latch comprising a D input and outputting a modulus signal, wherein the control step controls the D input.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 3, 2021
From: MEDIATEK INC.
To: XUESHAN TECHNOLOGIES INC.
Reel/Frame 055486/0870 →
MERGER Recorded Jun 12, 2020
From: MSTAR SEMICONDUCTOR, INC.
To: MEDIATEK INC.
Reel/Frame 052931/0468 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 24, 2012
From: CHEN, YEN-TSO; DING, JIAN-YU
To: MSTAR SEMICONDUCTOR, INC.
Reel/Frame 028622/0724 →