IP Library Granted Patent US 8,599,055
Granted Patent B1
US 8,599,055 · App. 13/556,414 · Granted Dec 3, 2013

Digital-to-analog converter

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Quick Facts
Patent No.
US 8,599,055
App. No.
13/556,414
Granted
Dec 3, 2013
Kind
B1
Abstract

A digital-to-analog converter ( 10 ) is described which comprises at least one cell ( 301 ). The cell ( 301 ) has a first coupling capacitor ( 415 ) with a second terminal connected to an output and a first inverter ( 405, 410 ) connected between a bias voltage and ground. The gates of the field effect transistors ( 405, 410 ) forming the first inverter are connected to a data input ( 305 ) and a first common point between the field effect transistors ( 405, 410 ) is connected to a first terminal of the first coupling capacitor ( 415 ).

Claims (33)

1. A digital-to-analog converter comprising at least one cell, the at least one cell having:

a first coupling capacitor with a second terminal connected to an output;

a first inverter connected between a bias voltage and ground, wherein gates of the first inverter are connected to a data input and a first common point is connected to a first terminal of the first coupling capacitor;

a second inverter connected between the bias voltage and ground, wherein the gates of the second inverter are connected to an inverted data input and a second common point is connected to a first terminal of a second coupling capacitor;

a differential output connected to a second side of the first coupling capacitor and a second side of the second coupling capacitor, wherein the differential output of at least one of the cells comprises

a third capacitor connected between the second side of the first coupling capacitor and ground;

a fourth capacitor connected between the second side of the second coupling capacitor and RF ground; and

an inductor connected between the second side of the first coupling capacitor and the second side of the second coupling capacitor and having a RF ground tap.

2. The digital-to-analog converter of claim 1 , wherein

the bias voltage is a supply voltage.

3. The digital-to-analog converter of claim 1 , wherein

the first inverter is a push-pull switch-mode power amplifier.

4. The digital-to-analog converter of claim 3 , wherein

the push-pull switch-mode power amplifier is realized using at least one of discrete or integrated MOS, JFET, MESFET or HEMT transistors.

5. The digital-to-analog converter of claim 1 , where the inductor comprises

a first inductor connected between the second side of the first coupling capacitor and ground; and

a second inductor connected between the second side of the second coupling capacitor and ground; wherein

one terminal of the first inductor, one terminal of the second inductor and ground are commonly connected.

6. The digital-to-analog converter of claim 1 having a plurality of cells with the outputs being commonly connected.

7. The digital-to-analog converter of claim 2 having a plurality of cells with the differential outputs being commonly connected.

8. A delta sigma modulator comprising:

an input connected to at least one first transconductance element having an output connected to a node;

at least one resonator connected to the node;

at least one digital-to-analog converter with an output being connected to the node;

at least one second transconductance element with an input connected to the node and an output connected to an analog-to-digital converter; and

a feedback loop connected between the output of the analog-to-digital converter and the input of the at least one digital-to-analog converter, wherein the digital to analog converter comprises at least one cell, the at least one cell having:

a first coupling capacitor with a second terminal connected to the output;

a first inverter connected between a bias voltage and ground, and wherein gates of the first inverter are connected to a data input and a first common point is connected to a first terminal of the first coupling capacitor;

a second inverter connected between the bias voltage and ground, wherein the gates of the second inverter are connected to an inverted data input and a second common point is connected to a first terminal of a second coupling capacitor;

a differential output connected to a second side of the first coupling capacitor and a second side of the second coupling capacitor, wherein the differential output of at least one of the cells comprises

a third capacitor connected between the second side of the first coupling capacitor and ground;

a fourth capacitor connected between the second side of the second coupling capacitor and RF ground; and

an inductor connected between the second side of the first coupling capacitor and the second side of the second coupling capacitor and having a RF ground tap.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2020
From: ERICSSON AB
To: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
Reel/Frame 053816/0791 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 17, 2020
From: KATHREIN SE
To: ERICSSON AB
Reel/Frame 053798/0470 →
RELEASE OF SECURITY INTEREST Recorded Oct 24, 2019
From: COMMERZBANK AKTIENGESELLSCHAFT
To: KATHREIN SE; KATHREIN INTELLECTUAL PROPERTY GMBH
Reel/Frame 050817/0146 →
CONFIRMATION OF GRANT OF SECURITY INTEREST IN U.S. INTELLECTUAL PROPERTY Recorded Sep 20, 2018
From: KATHREIN SE (SUCCESSOR BY MERGER TO KATHREIN-WERKE KG)
To: COMMERZBANK AKTIENGESELLSCHAFT, AS SECURITY AGENT
Reel/Frame 047115/0550 →
MERGER AND CHANGE OF NAME Recorded Sep 19, 2018
From: KATHREIN-WERKE KG; KATHREIN SE
To: KATHREIN SE
Reel/Frame 047114/0982 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 29, 2013
From: UBIDYNE, INC.
To: KATHREIN-WERKE KG
Reel/Frame 031500/0547 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2012
From: KARTHAUS, UDO
To: UBIDYNE, INC.
Reel/Frame 028660/0828 →