Granted Patent B2

US 8,853,798 · App. 13/556,676 · Granted Oct 7, 2014

Abstract

Claims (24)

1. An integrated circuit comprising:

a substrate carrying a plurality of circuit elements;

a metallization stack interconnecting said circuit elements, said metallization stack comprising a patterned upper metallization layer comprising a first metal portion and a second metal portion;

a passivation stack covering the metallization stack;

a gas sensor including a sensing material portion on the passivation stack;

a first conductive portion extending through the passivation stack connecting a first region of the sensing material portion to the first metal portion; and

a second conductive portion extending through the passivation stack connecting a second region of the sensing material portion to the second metal portion.

2. The integrated circuit of claim 1 , wherein the sensing material comprises a porous layer comprising at least one metal oxide.

3. The integrated circuit of claim 2 , wherein the porous layer is a substrate layer functionalized with said at least one metal oxide.

4. The integrated circuit of claim 3 , wherein the at least one metal oxide is one of ZnO and Al 2 O 3 .

5. The integrated circuit of claim 2 , wherein the porous layer comprises anodic aluminum oxide.

6. The integrated circuit of claim 1 , wherein the sensing material portion comprises a T-shape such that a recess is located between the sensing material portion and the passivation stack.

7. The integrated circuit of claim 1 , wherein sidewalls of the sensing material portion are separated from the first and second conductive portions by respective electrically insulating sidewall spacers.

8. The integrated circuit of claim 1 , wherein the first and second conductive portions comprise respective bond wires.

9. The integrated circuit of claim 1 , further comprising:

a heating element in a metallization layer of the metallization stack, said heating element being located opposite the sensing material portion.

10. The integrated circuit of claim 1 , wherein the sensing material is patterned with lithographic and deposition techniques so that only the portion of the sensing material deposited remains on the passivation stack.

11. The integrated circuit of claim 1 , wherein the sensing material includes a track extending between the first and second conductive portions which shorts the sensing material.

12. The integrated circuit of claim 11 , wherein the track is a metal track formed by incomplete processing of the sensing material.

13. The integrated circuit of claim 1 , further comprising:

a recess between the sensing material portion and the passivation stack, whereby the recess prevents a short-circuit of the sensing material portion.

14. The integrated circuit of claim 1 , further comprising:

an insulating sidewall spacer between sidewalls of the sensing material portion and at least one of the conductive portions, whereby the spacer prevents a short-circuit of the sensing material portion.

15. The integrated circuit of claim 1 , wherein at least one of the conductive portions is a bond-wire which does not contact sidewalls of the sensing material portion, whereby the bond-wire prevents a short-circuit between the conductive portions.

Assignments (12)