Method of operating a CMOS APS pixel sensor

1. A method of operating a pixel circuit, comprising:

biasing a reset transistor source/drain of a first pixel with a first voltage source on a first line;

biasing a source follower transistor source/drain of a second pixel with the first voltage source on the first line;

biasing a reset transistor source/drain of the second pixel with a second voltage source on a second line;

during a reset of the second pixel, dropping the first voltage source to ground; and

controlling the reset transistor of the first pixel by a signal pulsed on a third line.

2. A method as in claim 1 , wherein said resetting of the second pixel comprises pulsing a signal on a shared reset/select line connected to the gate of the reset transistor of the second pixel and a gate of a select transistor of a third pixel.

3. A method as in claim 1 , further comprising:

raising the first voltage source during the reset a reference sampling of the second pixel.

4. A method as in claim 1 , further comprising:

prior to said reset, reading out a pixel signal sample by pulsing a signal on a shared reset/select line connected to the gate of a select transistor of the second pixel and the gate of the reset transistor of the first pixel.

5. A method as in claim 1 , further comprising:

subsequent to said reset, reading out a reference voltage by pulsing a signal on a shared reset/select line connected to the gate of a select transistor of the second pixel and the gate of the reset transistor of the first pixel.

6. A method of operating a CMOS imager pixel sensor circuit, comprising:

biasing a reset transistor source/drain of a first pixel with a first voltage signal supplied to a first row of pixels;

biasing a source follower transistor source/drain of a second pixel, associated with a second row of pixels that at least partially overlaps the first row of pixels, with a voltage source on a first line;

biasing a reset transistor source/drain of the second pixel with a second voltage signal on a second line electrically isolated from the first line;

during operation of the pixel circuit, lowering the first voltage signal; and

controlling the reset transistor of the first pixel by a time-pulsed signal on a third line.

7. The method of claim 6, wherein the second voltage signal is different from the voltage source.

8. The method of claim 6, wherein the voltage source is the first voltage signal.

9. The method of claim 6, further comprising lowering the first voltage signal after sampling the first pixel and before sampling the second pixel.

10. The method of claim 6, further comprising providing a boosted voltage to a plurality of reset transistors of a plurality of pixels of the pixel circuit.

11. The method of claim 6 where the second voltage signal is the first voltage signal delayed by a period of time.

12. The method of claim 6 wherein the reset transistor source/drain of the first pixel is different from the reset transistor source/drain of the second pixel.