Integrated circuit
View Patent ↗An integrated circuit comprising a Class-D amplifier for amplifying an input signal at an input terminal is disclosed. The Class-D amplifier is switchable between an operational mode, in which a comparator ( 4 ) is directly coupled to an output stage ( 5 ), and a test mode, in which the comparator ( 4 ) is coupled to the output stage ( 5 ) via a sampler ( 15 ) and the output stage ( 5 ) is coupled to the input terminal via a feedback network, whereby a digital representation of the input signal is available at an output of the sampler ( 15 ).
1. An integrated circuit comprising a Class-D amplifier for amplifying an input signal at an input terminal, the Class-D amplifier being switchable between an operational mode, in which a comparator is directly coupled to an output stage, and a test mode, in which the comparator is coupled to the output stage via a sampler and the output stage is coupled to the input terminal via a feedback network, whereby a digital representation of the input signal is available at an output of the sampler.
2. An integrated circuit according to claim 1 , wherein the output stage is coupled to an output terminal.
3. An integrated circuit according to claim 1 , further comprising an input digital-to-analogue converter (DAC) with an output coupled to the input terminal.
4. An integrated circuit according to claim 3 , wherein the output of the sampler is coupled to an input of the input DAC and the output stage is coupled to a ground terminal via a switch.
5. An integrated circuit according to claim 4 , wherein the output of the sampler is coupled to an input of the input DAC via a buffer.
6. An integrated circuit according to claim 5 , wherein the buffer is an inverting buffer.
7. An integrated circuit according to claim 1 , further comprising a low-pass filter between the input terminal and the comparator.
8. An integrated circuit according to claim 7 , wherein the low-pass filter is a second order low-pass filter.
9. An integrated circuit according to claim 1 , wherein the feedback network is a resistor coupled from the output stage to the input terminal.
10. An integrated circuit according to claim 1 , wherein the sampler is driven by a clock running at an oversampling frequency.
11. An integrated circuit according to claim 1 , further comprising a digital signal processor (DSP) for receiving the digital representation at the output of the sampler and analysing the received digital representation in accordance with a predetermined test protocol.
12. A method of testing an integrated circuit according to claim 1 , the method comprising:
switching the integrated circuit into the test mode,
coupling a test signal to the input terminal,
receiving the digital representation at the output of the sampler, and
analysing the output signal in accordance with a predetermined test protocol.
13. A method of testing an integrated circuit according to claim 12 , wherein the predetermined test protocol includes analyses of the signal-to-noise ratio (SNR), total harmonic distortion (THD) and power supply rejection (PSR).
14. A method of testing an integrated circuit according to claim 12 , wherein the analysis of the output signal in accordance with the predetermined test protocol is performed by a digital signal processor (DSP) integrated on the integrated circuit.