IP Library Granted Patent US 8,895,335
Granted Patent B1
US 8,895,335 · App. 13/558,516 · Granted Nov 25, 2014

Impurity-induced disorder in III-nitride materials and devices

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Quick Facts
Patent No.
US 8,895,335
App. No.
13/558,516
Granted
Nov 25, 2014
Kind
B1
Abstract

A method for impurity-induced disordering in III-nitride materials comprises growing a III-nitride heterostructure at a growth temperature and doping the heterostructure layers with a dopant during or after the growth of the heterostructure and post-growth annealing of the heterostructure. The post-growth annealing temperature can be sufficiently high to induce disorder of the heterostructure layer interfaces.

Claims (14)

1. A method for impurity-induced layer disordering in III-nitride materials, comprising:

growing a III-nitride heterostructure at a growth temperature chosen to prevent layer disordering

and doping one or more of the heterostructure layers with an impurity during growth, and

post-growth annealing the heterostructure at an annealing temperature, time, and carrier gas pressure that induces disorder of one or more the heterostructure layer interfaces.

2. The method of claim 1 , wherein the III-nitride heterostructure comprises a plurality of AlGaN/AlN, GaN/AlN, GaN/AlGaN, InGaN/GaN, InGaN/AlN, InGaN/AlGaN, AlInN/GaN, AlInN/AlN, or AlInN/InGaN layers.

3. The method of claim 1 , wherein the impurity comprises silicon, magnesium, selenium, or tellurium.

4. The method of claim 1 , wherein the dopant concentration in the heterostructure is greater than 5×10 19 cm −3 .

5. The method of claim 1 , wherein the growing comprises metal-organic vapor phase epitaxy, molecular beam epitaxy, or vapor phase epitaxy.

6. The method of claim 1 , wherein the growth temperature is less than 885° C.

7. The method of claim 1 , wherein the annealing temperature is greater than 700° C.

8. The method of claim 7 , wherein the annealing temperature is greater than 1000° C.

9. The method of claim 1 , wherein the carrier gas comprises N 2 , NH 3 , H 2 , or He.

10. The method of claim 1 , further comprising depositing a dielectric layer on a portion of the surface of the doped heterostructure prior to the post-growth annealing.

11. The method of claim 10 , wherein the dielectric layer comprises SiN, SiON, or SiO 2 .

Assignments (3)
CHANGE OF NAME Recorded May 22, 2018
From: SANDIA CORPORATION
To: NATIONAL TECHNOLOGY & ENGINEERING SOLUTIONS OF SANDIA, LLC
Reel/Frame 046871/0595 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 29, 2013
From: WIERER, JONATHAN J., JR.; ALLERMAN, ANDREW A.
To: SANDIA CORPORATION
Reel/Frame 031499/0858 →
CONFIRMATORY LICENSE Recorded Sep 6, 2013
From: SANDIA CORPORATION
To: U.S. DEPARTMENT OF ENERGY
Reel/Frame 031182/0435 →